SU1008731A1 - Computing device - Google Patents

Abstract

COMPUTATIONAL DEVICE containing two registers, two first stage decoders, second stage decoder, two blocks of OR elements, result encoder, analyzer zero values of operands, the outputs of the first and second registers are connected to the first inputs of the first and second decoders of the first stage, respectively, whose outputs are , dinene, respectively, with the first and second inputs of the second stage decoder, the output of which is connected to the inputs of blocks of OR elements, the outputs of which are connected respectively to the first and the second inputs of the result encoder, the third input of which is connected: to the bus, specifying the operating mode of the device, outputs, the first and second registers are connected respectively to the first and second inputs of the analyzer zero operands, the first and second outputs of which are zero outputs respectively. the results of multiplying and adding the device, the third output of the zero analyzer of the operands is connected to the fourth input of the result encoder, the output of which is the output of the device, characterized in that It extends the functionality by summing two decimal digits and input transfer digits, it contains an input transfer analyzer, the outputs of the first and second registers are connected respectively to the first and second inputs of the input transfer analyzer, the third input of which is connected to the input transfer bus of the device and the third input (About the analyzer zero values of the operands, the first and second outputs of the input transfer analyzers are connected respectively with the second first and second first decoder of the first stage, the third output of the input transfer analyzer is connected to the input of the result encoder. 2. The device according to claim 1, wherein the analyzer includes two input transfer. And, two elements OR, the first inputs of the first AND elements and OR are connected to the first input of the analyzer, the second inputs of the first AND elements and OR are connected to the output of the second AND element, the outputs of the first AND and OR elements are respectively the third and first outputs analyzer, the first inputs of the second elements AND and OR are connected to the second input of the analyzer, the second inputs of the second elements AND and OR are connected to the third input of the analyzer.

Description

the output of the second element OR is the second output of the analyzer,

3. The device according to claim 1, characterized in that the analyzer of zero values of the operands contains eleven elements AND and element OR, the first input of the analyzer is connected to the inputs from the first to the fourth of the first element AND, the second input of the analyzer is connected to the inputs of the second element AND from the first on the fourth, the first input of the analyzer is connected to the first inputs of the elements And from the third to the sixth, the second inputs of which are connected to the output of the second element And, the second input of the analyzer is connected to the first inputs of the elements And from the seventh to the tenth, W The second inputs of which are connected to the output of the first element AND, the outputs of the first and second elements AND are connected to the inputs of the element OR and the eleventh element AND, the third input of the analyzer is connected to the fifth inputs of the first and second elements AND, the outputs of the element OR and the eleventh element AND are respectively The first and second outputs of the analyzer, the outputs of the elements And from the third to the tenth are the third output of the analyzer.

k. A device according to claim 1, characterized in that the result encoder contains thirteen OR elements, eight AND elements, the NOT element, the outputs of the first through eighth elements of the encoder output, and their first inputs are connected respectively to the outputs of the OR elements from first to the eighth, the first inputs of which are connected to the first input of the encoder, the second inputs of elements AND from the first to the third are connected to the first inputs of elements OR from ninth to thirteenth, the input of elements NOT and the third input of the encoder, the second inputs of elements AND from the eighth to the eighth are connected respectively to the outputs of the OR elements from the ninth to the thirteenth, the second inputs of which are connected to the second input of the encoder, the third inputs of the elements OR from the tenth to the thirteenth are connected to the fourth input of the encoder, the fifth input of which is connected to the fourth input of the thirteenth element OR , the second inputs of the elements OR from the fourth to the eighth are connected to the output of the element NOT.

The invention relates to computing technology and can be used in the construction of decimal arymetric devices. A device for multiplying decimal digits containing a multiplier register, a multiplier generating unit, a control unit, an additional register, whose information inputs are connected to information outputs of the lower tetrads of the multiplier forming unit, whose information inputs of the higher tetrads are connected to the outputs of the additional register, is known. The input of which is connected to the fifth output of the control unit L. The disadvantages of the known devices are the low speed and low functionality that ensures the execution of only the multiplication operation. Matrix devices are also known to multiply and add decimal digits, each of which contains two decoders, a matrix of elements AND, and an encoder, the inputs of the decoders are connected to the corresponding inputs of devices, the outputs of the encoders are outputs of devices 2J. The disadvantages of these devices are the large hardware costs, a significant part of which is made up of the matrixes of the AND elements, as well as their narrow specialization (performing either addition or only multiplication). The closest to the proposed technical entity is a matrix computing device containing two registers, two decoders, a matrix of AND elements, two blocks of OR elements, an array of operands, and an equality block of operands. two encoders, with the outputs of the first and second registers connected to the inputs of the first and second, respectively. decoders whose outputs are connected to the corresponding groups of inputs of the operand placement block and operands equality block, the inputs of the matrix of elements And are connected to the corresponding outputs of the blocks of the arrangement of operands, and outputs to the corresponding first groups of inputs of the first and second blocks of elements OR the second groups of inputs of which are connected with the corresponding outputs of the equality block of the operands, and the outputs of the first m of the second block of the OR elements are respectively connected from the input of the first to the second encoder, the outputs of which Are the first and the first group of device outputs. This device allows you to perform the operations of adding and multiplying decimal digits for. The disadvantage of this device is performing in it the addition of two decimal digits of the accounting base for the digit of the input transfer, which leads to a significant increase in hardware costs when building multi-decimal fixes Based on it. The purpose of the invention is to expand the functionality of the device by performing a summation operation of two decimal digits and a number of input transfer. The goal is achieved by those. That a computing device contains two registers, two first-stage decoders, a second-stage decoder, two blocks of OR elements, an encoder of the result, an analyzer of zero operand values, with output1 of the first and second registers connecting to the first and second decoders of the first and second decoders of the first and second registers. step, the outputs of which are connected respectively to the first and second inputs of the second stage decoder, the output of which is connected to the inputs of blocks of the OR elements, the outputs of which are connected to COOTBet, but to the first and the second The third inputs of the result encoder, the third input of which is connected to the device operation mode setting bus, the outputs of the first and second registers are connected respectively to the first and second inputs of the zero operand analyzer, the first and second outputs of which are, respectively, outputs of zero multiplication and addition of the device, the third The zero / value analyzer output of the NII operands is connected to the fourth input of the result encoder, the output of which is the output of the device. contains the input transfer analyzer, and the outputs of the first and second registers are connected respectively to the first and second inputs of the input transfer analyzer, the third input of which is connected to the input transfer bus of the device and the third input of the operand zero analyzer, the first and second inputs of the input transfer analyzer are respectively connected with the second the inputs of the first and second decoders of the first stage, the third output of the input transfer analyzer is connected to the fifth input of the result encoder. The goal is achieved by the fact that the input transfer analyzer contains two AND elements, two OR elements, and the first inputs of the first AND elements OR are connected to the first input of the analyzer, the second inputs of the first AND elements and OR are connected to the output of the second AND element, and OR are the third and first analyzer outputs, the first, the inputs of the AND and OR elements are connected to the second input of the analyzer, the second inputs of the second elements AND and OR are connected to the third input of the analyzer, the output of the second is The OR element is the second output of the analyzer. In addition, the goal is achieved by the fact that the analyzer of zero values of operands contains oneiaAUaTb elements AND and an OR element, with the first input of the analyzer connected to the inputs from the first to the fourth of the first element AND, the second input of aHai analyzer is connected to the input of the second element AND from the first to the fourth, The first input of the analyzer is connected to the first inputs of elements I from the third to the sixth, the second inputs of which are connected to the output of the second element I, the second input of the analyzer is connected to the inputs of elements I from the seventh to the tenth, the second the inputs of which are connected to the output of the first element AND, the outputs of the first and second elements AND are connected to the inputs of the element VI and the eleventh element AND, the third input of the analyzer is connected to the fifth inputs of the first and second elements AND, the outputs of the element OR and the eleventh element AND are respectively the first and the second outputs of the analyzer, the outputs of the elements And from the third to the tenth are the third output of the analyzer. In addition, the goal is achieved in that the cut encoder contains thirteen OR elements, eight AND elements, the element NOT and the first through eighth element outputs are the encoder output, and their first inputs are connected, respectively, to the element outputs OR from first to eighth the eighth, the first inputs of which are connected to the first input of the encoder, the second inputs of the elements AND from the first to the third are connected to the first inputs of the elements OR from the ninth to the thirteenth, the input of the element NOT and the third input of the encoder, the second inputs of the element And from the fourth to the eighth are connected respectively with the outputs of the elements OR from the ninth ho the thirteenth, the second inputs of which are connected to the second input of the encoder, the third inputs of the elements OR from the tenth to the thirteenth are connected to the fourth input of the encoder, the fifth input of which is connected to the fourth input the thirteenth element OR, the second inputs of the elements OR from the fourth to the eighth are connected to the output of the element NOT. FIG. 1 shows a block diagram of a computing device / FIG. 2 is a functional diagram of the input transfer analyzer / in FIG. 3 is a functional diagram of an analyzer of zero values of operands, fig. C - functional result cipher scheme. The computing device contains the first and second registers 1 and 2, the first and second decoders 3 and i of the first stage, the decoder 5 of the second stage, block 6 elements OR multiplication operations, input transfer bus 7, input translate analyzer 8, operand zero analyzer 9, a block of 10 elements OR the operation of addition and the encoder 11 of the result. The input transfer analyzer 8 contains the first elements AND and OR 12 and 13 and the second elements AND and OR I) and 15. 316 The analyzer 9 zero values of the operands contains the elements AND from the first to the sixth 16-21, the element OR 22, and elements And from the seventh to the eleventh. The encoder 11 of the result contains the elements OR from the first to the thirteenth 28-40, the element is NOT 1 and the element AND from the first to the eighth. Four-bit registers 1 and 2 are designed to store decimal digits. The block 6 of the elements OR of the multiplication operation serves to reduce the cost of the equipment for converting the product represented in the unitary code into the binary-decimal code. It contains OR elements by which the outputs of the second stage decoder 5 are combined, generating the same multiplication results. The block 10 of the elements OR of the addition operation serves to reduce the equipment costs of converting the sum represented in the unitary code into the binary-decimal code. It contains the OR elements, by which the outputs of the elements and the second stage decoder 5 are combined, generating the same results of the addition of two decimal digits. Block 6 and 10 of the OR elements are the first steps of the encoders of the digits and sum digits, respectively, the second step of which are the OR entries of the result encoder 11, by which the binary digits of the multiplication and addition results and the digit of the transfer to the next decimal digit are formed. The input transfer analyzer 8 is designed to analyze the lower binary digits of the first and second decimal tetrads with and without input transfer. The analyzer 9 zero values of the operands is designed to test for the equality of the zero operands and the generation of the result and the corresponding features when one or two operands are zero. The result encoder 11 is designed to form the result of a multiply or add operation depending on the state of the control bus. The device operates as follows. 7 The source tetrads Xj, X2, X, X, and Xc, X, Hu, Xd, representing dec ten digits in binary code, are sent respectively to the inputs of the first and second input registers 1 and 2, from the outputs of which are three binary digits Operands Xc, X, X and Xg, X, XY are received respectively at the inputs of the first and second decoder 3 and% of the first stage, and the lower binary digits of both tetrads X and Xg go respectively to the first and second inputs of the analyzer 8 input transfer, to the third the input of which through bus 7 of the input transfer comes PCF pa input transfer HF, Combination a carry input analyzer circuit 8 operates in four rezhimah-. In the first mode, the input transfer. In this case, the input transfer analyzer generates the following signals: Z X -Xg-Xg 0Zj,. From the output of the element OR 13 of the analyzer 8, the input transfer of the lower double digit of the first decimal notebook arrives at the input of the lower order of the first decoder 3 first level, and from the output of the OR element 15 the lower binary digit of the second decimal tetrad Xg goes at the input the second order of the second decoder is 4 first steps. In the second mode, the input transfer is (the binary digit of the first decimal tetrad is younger), (the papse is the binary number of the second decimal tetra rad),. The analyzer 8 generates the following signals: 1 4 Xg, Zj X4VXg.X, 0; Z5 XgvXq 1. A single signal from the output of the element OR 15 analyzer 8 input transfer is fed to the input of the lower bit of the second decoder 4 of the first stage. In the third mode, the input is carried, the binary is the binary of the first decimal tetrad, and the binary is the binary of the second decimal tetrad. The input transfer analyzer 8 implements the following signals: Z, X «4.XeX9 0; 31 Xg-, XQVX, I. A single signal from the output of the element OR 13 is fed to the input of the lower bit of the first decoder 3 of the first stage, and the output of the element OR 15 is fed to the input of the lower category of the second decoder k of the first stage. Similar combinations of output signals are generated by input transfer analyzer 8 under conditions,. In the fourth mode, the input transfer is lower than the binary number of the first decimal tetrad. X (the younger binary digit of the second decade tetrad. The output signals implemented by the analyzer 8 are as follows: X4-X8 AgVX (. A single signal from the output of the And 12 element of the analyzer -8 input transfer is fed to the corresponding input of the element OR 40 that forms the youngest bit amount from the output of the element OR 13 a single signal is fed to the input of the lower bit of the first decoder 3 first stage, from the output of the element OR 15 analyzer 8 input transfer a single signal is fed to the input of the lower bit of the second decoder k first At the same time as the signals to the inputs of the input transfer analyzer 8 are input from the input registers 1 and 2, the numbers of the source tetrads and the input transfer numbers are sent to the corresponding inputs of the analyzer 9 zero operand values.Also, if the first decade is zero and there is no input transfer , then at the output of the AND 16 element with the inverse input for the transfer signal, a single signal appears and the second decimal transmission is allowed. The tetradas through the AND 23-26 elements to the corresponding inputs of the OR elements forming the digit Amount bits. Whether its second decadic tetrad is null and there is no input transfer, then a single signal appears at the output of AND 17 and the transfer of the first decimal tetrad through AND 18-21 elements to the corresponding inputs of OR elements that form digits, bits of the sum . In these cases, the function (i at the output of the element OR 22 (Fig. 3) takes a single value, which corresponds to the development of a sign-zero multiplication result. This sign is fed to the corresponding control input of the result receiver as an informative signal. In case of both decimal tetrads are zero and there is no input transfer, at the output of the elements 16 and 17 there appear single signals and accordingly the signal 11 at the output of the element 27 takes a single value, which corresponds to the development of the sign of the zero result from the outputs of the first and second decoders 3 and 4 of the first stage of virgins; tic words in the unitary code (i.e., the decoded digits from 1 to 9) go to the inputs of the decoder of the second stage from the output of which the words in the unitary code are fed to the inputs of blocks 10 and 6 elements OR, from the outputs of which the same results of adding and multiplying two decimal digits and the unitary code are received respectively at the information inputs of the elements OR З40 and 28-35 ciprato ra 11 results. The device operates in two modes: add and multiply. In the addition mode, a zero signal arrives at the control input of the result encoder 11, which is fed to one of the inputs of each element in the line of OR elements that form the digits of the sum without making any changes in the modal works. At the same time, the same signal is applied to output elements AND 2-, overlapping the output circuits of the three higher digits of the result that are not needed in the mode of addition. forming the lowest five digits of the product. As a result, single signals are generated at the output of these elements OR, which is tantamount to interrupting the output circuits of five lower digits of the product. . Single signals are fed to the inputs of output elements AND, to the other inputs of which the digits of the elements are received from the elements OR. Thus, the five-tyrant sum (binary tetrad and transfer signal to the next tetrad) will be output from the AND 29 line of output elements to the corresponding information inputs of the result receiver. In multiplication, the control input of the result encoder 11 is given a single signal), which is fed to one of the inputs of each element in the OR element array. actually interrupts their work, generating single units on their outputs. At the same time, the same signal is sent to output elements AND 4244, preparing them for receiving and issuing three higher digits of the product from the elements OR 28-30. Single signals from the OR elements 36-40 are fed to the inputs of the output elements 45-49, preparing them for receiving and issuing five lower digits of the product from the elements OR 31-35. Thus, an eight-bit product (two binary tetrads) will be issued from the output element ruler AND 42-49 to the device outputs, and from them to the corresponding information inputs of the result receiver. The efficiency of the proposed computing device in comparison with the known ones is in extending the functionality by performing the operation of summing up decimal digits and numbers of the input-, leg of the transfer, which allows building on its basis multi-decimal arithmetical devices with higher speed and requiring less hardware costs for implementation.

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Claims (4)

A COMPUTER DEVICE containing two registers', two decoders of the first stage, a decoder of the second stage, two blocks of OR elements, a result encoder, an analyzer of zero operand values, the outputs of the first and second registers are connected respectively to the first inputs of the first and second decoders of the first stage the outputs of which are connected respectively with the first and second inputs of the second stage decoder, the output of which is connected to the inputs of the blocks of elements OR, the outputs of which are connected respectively with the first and second the inputs of the result encoder, the third input of which is connected to the bus for setting the device operation mode, the outputs of the first and second registers are connected respectively to the first and second inputs of the analyzer of zero values of operands, the first and second outputs of which are respectively the outputs of zero results of multiplication and addition of the device , the third output of the analyzer of zero values of the operands is connected to the fourth input of the result encoder, the output of which is the output of the device, characterized in that, in order to expand functionality by summing two decimal digits and an input transfer digit, it contains an input transfer analyzer, and the outputs of the first and second registers are connected respectively to the first and second inputs of the input transfer analyzer, the third input of which is connected to the input transfer bus of the device and the third input analyzer of zero values of operands, the first and second outputs of the input Transfer analyzers are connected respectively to the second inputs of the first and second decoders of the first of the first stage, the third output of the input transfer analyzer is connected to the fifth input of the result encoder. 2. The device according to claim 1, wherein the input transport analyzer contains two. AND element, two OR elements, with the first inputs of the first AND and OR elements connected to the first input of the analyzer, the second inputs of the first AND and OR elements connected to the output of the second AND element, the outputs of the first AND and OR elements are the third and first outputs of the analyzer, respectively the first inputs> of the second AND and OR elements are connected to the second input of the analyzer, the second inputs of the second AND and OR elements are connected to the third input of the analyzer,> the output of the second OR element is the second output of the analyzer. 3. The device according to claim 1, characterized in that the analyzer of zero values of the operands contains eleven AND elements and an OR element, the first input of the analyzer connected to the inputs from the first to the fourth first AND element, the second input of the analyzer connected to the inputs of the second AND element from the first the fourth, the first input of the analyzer is connected to the first inputs of the elements And from the third to the sixth, the second inputs of which are connected to the output of the second element And, the second input of the analyzer is connected to the first inputs of the elements And from the seventh to tenth, sec whose inputs are connected to the output of the first AND element, the outputs of the first and second elements Y are connected to the inputs of the OR element and the eleventh element AND, the third input of the analyzer is connected to the fifth inputs of the first and second elements AND, the outputs of the OR element and the eleventh element AND are respectively the first and the second outputs of the analyzer, the outputs of the elements And from the third to the tenth are the third output of the analyzer. 4. The device according to claim 1, characterized in that the result encoder contains thirteen OR elements, eight AND elements, an NOT element, and the outputs of the AND elements from the first to the eighth are the encoder output, and their first inputs are connected respectively to the outputs of the OR elements from the first in the eighth, the first inputs of which are connected to the first input of the encoder, the second inputs of the AND elements from the first to the third are connected to the first inputs of the OR elements from the ninth to the thirteenth, the input of the element NOT and the third input of the encoder, the second inputs of the elements AND from the fourth the third through the eighth are connected respectively to the outputs of the OR elements from the ninth to the thirteenth, the second inputs of which are connected to the second input of the encoder, the third inputs of the OR elements from the tenth to thirteenth are connected to the fourth input of the encoder, the fifth input of which is connected to the fourth input of the thirteenth OR element, the second inputs the fourth to eighth elements are connected to the output of the element NOT.