RU2758188C1 - Logic module - Google Patents

Abstract

FIELD: computing technology.

SUBSTANCE: disclosed is a logic module intended for implementation of simple symmetric Boolean functions, containing four majority elements, wherein the second and third inputs of the second majority element are connected with the output of the first majority element and the third information input of the logic module, respectively, the first, second information and the first configuration inputs whereof are connected to the second, third and first inputs of the first majority element, respectively, wherein two majority elements are additionally introduced thereto, the second, third inputs of the j^th

and the second input of the third majority elements are connected with the outputs of the (j-1)^th, (j-3)^th majority elements and the output of the second majority element, respectively, and the first, second, third, fourth inputs of the majority element and the third input of the third, the first input of the fifth majority elements are connected to the first, second, third and fourth information inputs of the logic module, respectively, the first, second, third configuration inputs and the output whereof are connected with the first inputs of the second, third, the first input and output of the sixth majority elements, respectively.

EFFECT: ensured implementation of simple symmetric Boolean functions.

1 cl, 1 dwg

Description

The invention relates to computer technology and can be used to build automation tools, functional units of control systems, etc.

Known logical modules (see, for example, RF patent 2249844, class G06F 7/38, 2005), which can be configured to implement any of the simple symmetric Boolean functions τ _{0.5 × (n + 1) -1} , τ _{0.5 × (n + 1)} , τ _{0.5 × (n + 1) +1} , depending on n arguments - input binary signals x ₁ , ..., x _n ∈ {0,1}, for n = 3 ...

The reason that impedes the achievement of the technical result indicated below when using known logical modules includes limited functionality and heterogeneity of the hardware composition, due, respectively, to the fact that the implementation of any of the functions τ _{0.5 × (n + 1) -1} , τ _{0 , 5 × (n + 1)} , τ _{0.5 × (n + 1) +1} for n = 5 and, in particular, the mentioned analogue contains logical elements of three types (AND, OR, majority elements).

The closest device for the same purpose to the claimed invention in terms of a set of features is a logic module adopted as a prototype (RF patent 2542920, class G06F 7/57, 2015), which contains four majority elements and can be configured to implement any of the simple symmetric Boolean functions τ _{0.5 × (n + 1) -1} , τ _{0.5 × (n + 1)} , τ _{0.5 × (n + 1) +1} , depending on n arguments - input binary signals x _1, …, X _n ∈ {0,1}, for n = 3.

The reason that prevents the achievement of the technical result indicated below when using the prototype includes limited functionality due to the fact that the implementation of any of the functions τ _{0.5 × (n + 1) -1} , τ _{0.5 × (n + 1 )} , τ _{0.5 × (n + 1) +1} for n = 5.

The technical result of the invention is the expansion of functionality by ensuring the implementation of any of the simple symmetric Boolean functions τ _{0.5 × (n + 1) -1} , τ _{0.5 × (n + 1)} , τ _{0.5 × (n + 1 ) +1} , depending on n arguments - input binary signals x ₁ , ..., x _n ∈ {0,1}, for n = 5 using the tuning set {0,1, x ₅ } while preserving the elementary basis of the prototype.

и второй вход третьего мажоритарных элементов соединены соответственно с выходами (j-1)-го, (j-3)-го мажоритарных элементов и выходом второго мажоритарного элемента, а первый, второй, третий входы четвертого мажоритарного элемента и третий вход третьего, первый вход пятого мажоритарных элементов подключены соответственно к первому, второму, третьему и четвертому информационным входам логического модуля, первый, второй, третий настроечные входы и выход которого соединены соответственно с первыми входами второго, третьего, первым входом и выходом шестого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logical module containing four majority elements, the second and third inputs of the second majority element are connected, respectively, to the output of the first majority element and the third information input of the logical module, the first, second information and first tuning inputs of which are connected respectively, to the second, third and first inputs of the first majority element, the peculiarity is that two majority elements are additionally introduced into it, the second, third inputs of the j-th

and the second input of the third majority element is connected, respectively, to the outputs of the (j-1) th, (j-3) th majority elements and the output of the second majority element, and the first, second, third inputs of the fourth majority element and the third input of the third, the first input of the fifth majority elements are connected, respectively, to the first, second, third and fourth information inputs of the logical module, the first, second, third tuning inputs and the output of which are connected respectively to the first inputs of the second, third, first input and output of the sixth majority elements.

The drawing shows a diagram of the proposed logic module.

и выход элемента 1_j-4 соединены соответственно с выходами элементов 1_j-1, 1j_-3 и вторым входом элемента 1_j-3, а второй вход элемента 1₁, первый вход элемента 1₅, i-й

вход элемента 1₄, третий вход элемента 1_i и выход элемента 1₆ подключены соответственно к первому, четвертому, i-му, (i+1)-му информационным входам и выходу логического модуля, первый и второй, третий настроечные входы которого соединены соответственно с первыми входами элементов 1₁, 1₂ и 1₃, 1₆.The logical module contains majority elements 1 ₁ , ..., 1 ₆ , and the second, third inputs of the element 1 _j

and the output of the element 1 _{j-4 are} connected, respectively, with the outputs of the elements 1 _j-1 , 1j _-3 and the second input of the element 1 _j-3 , and the second input of the element 1 ₁ , the first input of the element 1 ₅ , the i-th

the input of element 1 ₄ , the third input of element 1 _i and the output of element 1 _{6 are} connected, respectively, to the first, fourth, i-th, (i + 1) -th information inputs and the output of the logical module, the first and second, third tuning inputs of which are connected respectively with the first inputs of elements 1 ₁ , 1 ₂ and 1 ₃ , 1 ₆ .

имеем

где

и

есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И. Следовательно, сигнал на выходе элемента 1₆ определяется выражением

в котором

The proposed logic module operates as follows. _{Binary signals x 1} ,…, x ₄ ∈ {0,1} and y ₁ ,…, y ₃ ∈ {0,1} are fed to its first,…, fourth information and first,…, third setting inputs, respectively. At the output of the element

we have

where

and

there are, respectively, signals at its first, second, third inputs and symbols of operations OR, AND. Therefore, the signal at the output of element 1 ₆ is determined by the expression

in which

Thus, at the output of the proposed logical module, we obtain

where 0, 1, x ₅ are the elements of the tuning set; τ ₂ , 1 ₃ , 1 ₄ are simple symmetric Boolean functions of five arguments x ₁ , ..., x ₅ (see page 126 in the book: Pospelov D.A. Logical methods of analysis and synthesis of circuits. M .: Energiya, 1974 .).

The above information allows us to conclude that the proposed logic module is built on the element basis of the prototype and has wider functional capabilities compared to the prototype, since it implements any of the simple symmetric Boolean functions τ _{0.5 × (n + 1) -1} , τ _{0 , 5 × (n + 1)} , τ _{0.5 × (n + 1) +1} , depending on n arguments - input binary signals x ₁ , ..., x _n ∈ {0,1}, for n = 5. In this case, the tuning set {0,1, x ₅ } is used.

Claims (1)

A logical module designed to implement simple symmetric Boolean functions, containing four majority elements, the second and third inputs of the second majority element being connected respectively to the output of the first majority element and the third information input of the logical module, the first, second informational and first tuning inputs of which are connected respectively to the second, third and first inputs of the first majority element, characterized in that two majority elements are additionally introduced into it, the second, third inputs of the j-th

and the second input of the third majority element is connected, respectively, to the outputs of the (j-1) th, (j-3) th majority elements and the output of the second majority element, and the first, second, third inputs of the fourth majority element and the third input of the third, the first input of the fifth majority elements are connected, respectively, to the first, second, third and fourth information inputs of the logical module, the first, second, third tuning inputs and the output of which are connected respectively to the first inputs of the second, third, first input and output of the sixth majority elements.

Images