RU2629451C1 - Logic converter - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: logic converter is designed to perform any of the five simple symmetrical Boolean functions depending on the five arguments -input binary signals, and can be used in the systems of the digital computers as the code conversion tool. The logic converter comprises ten majority elements (1₁,…, 1₁₀).

EFFECT: reduction of the hardware costs.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical converters are known (see, for example, RF patent 2440601, class G06F 7/57, 2012), which contain majority elements and use any of five simple symmetric Boolean functions using three constant symmetric Boolean signals, depending on five arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using known logic converters includes high hardware costs, due to the fact that, in particular, the aforementioned analogue contains seventeen major elements.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2517720, class G06F 7/57, 2014), which contains major elements and implements any of five simple symmetric signals using three constant tuning signals Boolean functions depending on five arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using the prototype includes high hardware costs due to the fact that the prototype contains twelve major elements.

The technical result of the invention is to reduce hardware costs while maintaining the functionality of the prototype.

и шестого мажоритарных элементов соединены соответственно с вторыми входами (i+1)-го и восьмого мажоритарных элементов, выход седьмого и выход десятого мажоритарных элементов подключены соответственно к первому входу третьего и третьему входу восьмого мажоритарных элементов, а третий вход k-го

и выход четвертого мажоритарных элементов соединены соответственно с выходом (12-k)-го мажоритарного элемента и выходом логического преобразователя, первый и второй настроечные входы которого подключены соответственно к первому входу пятого мажоритарного элемента и объединенным первым входам первого, второго, шестого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logical converter containing ten majority elements, which have three inputs, a second input of the seventh, a first input of the fourth majority elements and the combined first inputs of the seventh, eighth, ninth majority elements are connected respectively to the output of the fifth majority element, the third and first tuning inputs of the logical Converter, the feature is that the outputs of the i-th

and the sixth majority elements are connected respectively to the second inputs of the (i + 1) -th and eighth majority elements, the output of the seventh and the output of the tenth majority elements are connected respectively to the first input of the third and third input of the eighth majority elements, and the third input of the kth

and the output of the fourth majority elements are connected respectively to the output of the (12-k) -th majority element and the output of the logic converter, the first and second tuning inputs of which are connected respectively to the first input of the fifth majority element and the combined first inputs of the first, second, sixth majority elements.

The drawing shows a diagram of the proposed logical Converter.

и

соединены соответственно с вторыми входами элементов 1_i+1 и 1_j+2, выход элемента 1₇ и выход элемента 1₁₀ подключены соответственно к первому входу элемента 1₃ и третьему входу элемента 1₈, а третий вход элемента

и выход элемента 1₄ соединены соответственно с выходом элемента 1_12-k и выходом логического преобразователя, третий, первый и второй настроечные входы которого подключены соответственно к первому входу элемента 1₄, объединенным первым входам элементов 1₅, 1₇, 1₈, 1₉ и объединенным первым входам элементов 1₁, 1₂, 1₆.The logical converter contains the majority elements 1 ₁ , ..., 1 ₁₀ , which have three inputs, and the outputs of the elements

and

connected respectively to the second inputs of the elements 1 _{i + 1} and 1 _{j + 2} , the output of the element 1 ₇ and the output of the element 1 _{10 are} connected respectively to the first input of the element 1 ₃ and the third input of the element 1 ₈ , and the third input of the element

and the output of element 1 _{4 are} connected respectively to the output of element 1 _12-k and the output of the logic converter, the third, first and second tuning inputs of which are connected respectively to the first input of element 1 ₄ , combined by the first inputs of elements 1 ₅ , 1 ₇ , 1 ₈ , 1 ₉ and the combined first inputs of the elements 1 ₁ , 1 ₂ , 1 ₆ .

константной настройки. На вторые входы элементов 1₁, 1₅, первый вход элемента 1₁₀; третьи входы элементов 1₁, 1₅, второй вход элемента 1₁₀; третьи входы элементов 1₂, 1₇, 1₁₀; вторые и третьи входы элементов 1₆, 1₉ подаются соответственно двоичные сигналы х₁; х₂; х₃; х₄ и х₅ (x₁, …, x₅ ∈{0,1}). На выходе мажоритарного элемента 1_m

имеем mаj(a _m1, а _m2, а _m3)=а _m1 а _m2∨а _m1 а _m3∨а _m2 а _m3, где а _m1, а _m2, а _m3 и ∨, • есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И. Следовательно, сигнал на выходе элемента 1₄ определяется выражениемThe work of the proposed logical Converter is as follows. On its first, second, third tuning inputs, the necessary signals are fixed accordingly

constant settings. To the second inputs of the elements 1 ₁ , 1 ₅ , the first input of the element 1 ₁₀ ; the third inputs of the elements 1 ₁ , 1 ₅ , the second input of the element 1 ₁₀ ; the third inputs of the elements 1 ₂ , 1 ₇ , 1 ₁₀ ; the second and third inputs of elements 1 ₆ , 1 ₉ are binary signals x ₁ , respectively; x ₂ ; x ₃ ; x ₄ and x ₅ (x ₁ , ..., x ₅ ∈ {0,1}). At the output of the majority element 1 _m

have maj (a _m1, and _m2, and _m3) = a _m1 and _m2 ∨ and _m1 and _m3 ∨ and _m2 and _m3, where a is _m1, and _m2, and _m3 and ∨, • have respectively the signals at its first, second, the third inputs and operation symbols OR, I. Therefore, the signal at the output of element 1 ₄ is determined by the expression

Таким образом, на выходе предлагаемого преобразователя получимwherein

Thus, at the output of the proposed Converter get

,

,

where τ ₁ , ..., τ ₅ are simple symmetric Boolean functions of the five arguments x ₁ , ..., x ₅ (see page 126 in the book Pospelov DA Logical methods of analysis and synthesis of circuits. M .: Energy, 1974). Moreover, the specified Converter contains ten majority elements.

The above information allows us to conclude that the proposed logical converter using three constant tuning signals implements any of the five simple symmetric Boolean functions, depending on five arguments - input binary signals, and has lower hardware costs compared to the prototype.

Claims (1)

A logic converter designed to implement any of five simple symmetric Boolean functions depending on five arguments - input binary signals, containing ten majority elements that have three inputs, the second input of the seventh, the first input of the fourth majority elements and the combined first inputs of the seventh, the eighth, ninth majority elements are connected respectively to the output of the fifth majority element, the third and first tuning inputs of the logical Converter, distinguishing the outputs of the i-th

and the sixth majority elements are connected respectively to the second inputs of the (i + 1) -th and eighth majority elements, the output of the seventh and the output of the tenth majority elements are connected respectively to the first input of the third and third input of the eighth majority elements, and the third input of the kth

and the output of the fourth majority elements are connected respectively to the output of the (12-k) -th majority element and the output of the logic converter, the first and second tuning inputs of which are connected respectively to the first input of the fifth majority element and the combined first inputs of the first, second, sixth majority elements.

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