RU2621376C1 - Logic module - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: logic module is designed to perform any of five simple symmetrical Boolean functions depending on five arguments - binary input signals, and can be used in systems of digital computers as code conversion means. Logic module comprises four AND element (1_1,…,1₄), four OR elements (2₁,…,2₄₎, four majority element (3₁,…,3₄₎ and three tuning inputs.

EFFECT: reduction of hardware costs and reduction of number of adjusting entries.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical modules are known (see, for example, RF patent 2286594, class G06F 7/57, 2006), which contain AND elements, OR elements, majority elements and, using a constant setting, implement any of four simple symmetric Boolean functions depending on from four arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using well-known logic modules is limited functionality, due to the fact that the implementation of any of the five simple symmetric Boolean functions does not work, depending on five arguments - input binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the logical module adopted for the prototype (RF patent 2472209, class G06F 7/57, 2013), which contains AND elements, OR elements, four major elements and with the help of a constant settings implements any of five simple symmetric Boolean functions depending on five arguments - input binary signals.

The reasons that impede the achievement of the technical result indicated below when using the prototype include high hardware costs due to the fact that the prototype contains five AND elements and five OR elements, and the presence of four tuning inputs.

The technical result of the invention is to reduce hardware costs and reduce the number of tuning inputs while maintaining the functionality of the prototype.

элемента И соединены соответственно с выходами первых элемента ИЛИ, элемента И и первым, вторым входами i-го элемента ИЛИ, второй вход и выход четвертого мажоритарного элемента подключены соответственно к выходу третьего мажоритарного элемента и выходу логического модуля, первый, второй и третий, четвертый информационные входы которого соединены соответственно с первым, вторым входами первого и первым, вторым входами второго элементов ИЛИ, особенность заключается в том, что третьи входы первого, второго и второй вход третьего мажоритарных элементов соединены соответственно с выходами вторых элемента ИЛИ, элемента И и выходом третьего элемента ИЛИ, второй вход и выход j-го

мажоритарного элемента подключены соответственно к выходу (j+2)-го элемента И и третьему входу (5-j)-го мажоритарного элемента, а первые входы второго, четвертого мажоритарных элементов и объединенные первые входы первого, третьего мажоритарных элементов подключены соответственно к первому, третьему и второму настроечным входам логического модуля, пятый информационный вход которого соединен с вторым входом четвертого элемента ИЛИ, подключенного выходом к второму входу третьего элемента И.The specified technical result in the implementation of the invention is achieved by the fact that in a logical module containing four AND elements, four OR elements and four majority elements, the first inputs of the third, fourth OR elements and the first, second inputs of the i-th

And element are connected respectively to the outputs of the first OR element, And element, and the first, second inputs of the i-th OR element, the second input and output of the fourth majority element are connected respectively to the output of the third majority element and the output of the logic module, the first, second and third, fourth information the inputs of which are connected respectively to the first, second inputs of the first and first, second inputs of the second OR element, the peculiarity is that the third inputs of the first, second and second input of the third majority ith elements are connected respectively to the outputs of the second OR element, AND element and the output of the third OR element, the second input and output of the jth

the majority element are connected respectively to the output of the (j + 2) -th AND element and the third input of the (5-j) -th majority element, and the first inputs of the second, fourth majority elements and the combined first inputs of the first, third majority elements are connected respectively to the first, the third and second training inputs of the logic module, the fifth information input of which is connected to the second input of the fourth OR element, connected by the output to the second input of the third element I.

The drawing shows a diagram of the proposed logical module.

соединены соответственно с выходами элементов 2₄, 2₁, 1₁ и первым, вторым входами элемента 2_i, третьи входы элементов 3₁, 3₂ и вторые входы элементов 3₃, 3₄ подключены соответственно к выходам элементов 2₂, 1₂ и 2₃, 3₃, второй вход и выход элемента 3_j

соединены соответственно с выходом элемента 1_j+2 и третьим входом элемента 3_5-j, а первые входы элементов 3₂, 3₄ и объединенные первые входы элементов 3₁, 3₃ подключены соответственно к первому, третьему и второму настроечным входам логического модуля, первый, второй, третий, четвертый, пятый информационные входы и выход которого соединены соответственно с первым, вторым входами элемента 2₁, первым, вторым входами элемента 2₂, вторым входом элемента 2₄ и выходом элемента 3₄.The logic module contains the elements AND 1 ₁ , ..., 1 ₄ , the elements OR 2 ₁ , ..., 2 ₄ and the majority elements 3 ₁ , ..., 3 ₄ , the second input of the element 2 ₃ , the first inputs of the elements 2 ₃ , 2 ₄ and the first , the second inputs of the element 1 _i ,

connected respectively to the outputs of the elements 2 ₄ , 2 ₁ , 1 ₁ and the first, second inputs of the element 2 _i , the third inputs of the elements 3 ₁ , 3 ₂ and the second inputs of the elements 3 ₃ , 3 _{4 are} connected respectively to the outputs of the elements 2 ₂ , 1 ₂ and 2 ₃ , 3 ₃ , second input and output of element 3 _j

connected respectively to the output of the element 1 _{j + 2} and the third input of the element 3 _5-j , and the first inputs of the elements 3 ₂ , 3 ₄ and the combined first inputs of the elements 3 ₁ , 3 _{3 are} connected respectively to the first, third and second training inputs of the logic module, the first, second, third, fourth, fifth information inputs and the output of which are connected respectively to the first, second inputs of the element 2 ₁ , the first, second inputs of the element 2 ₂ , the second input of the element 2 ₄ and the output of the element 3 ₄ .

равен «1» («0») только тогда, когда на двух или на всех входах этого элемента действуют сигналы, равные «1» («0»). Следовательно, если на первом входе элемента 3_i присутствует «1» («0»), то этот элемент будет выполнять операцию ИЛИ (И) над сигналами, действующими на его втором и третьем входах. Таким образом, на выходе предлагаемого модуля получимThe work of the proposed logical module is as follows. Binary signals x ₁ , ..., x ₅ ∈ {0,1} and y ₁ , y ₂ , y ₃ ∈ {0,1} are given to its first, ..., fifth information and first, second, third tuning inputs. Signal at the output of the majority element 3 _i

It is equal to “1” (“0”) only when signals equal to “1” (“0”) act on two or all inputs of this element. Therefore, if “1” (“0”) is present at the first input of element 3 _i , then this element will perform an OR (AND) operation on signals acting on its second and third inputs. Thus, at the output of the proposed module, we obtain

,

,

,

есть символы операций ИЛИ, И; τ₁,…,τ₅ есть простые симметричные булевые функции пяти аргументов x₁,…,x₅ (см. стр. 126 в книге Поспелов Д.А. Логические методы анализа и синтеза схем. - М.: Энергия, 1974).Where

,

there are symbols of operations OR, AND; τ ₁ , ..., τ ₅ are simple symmetric Boolean functions of the five arguments x ₁ , ..., x ₅ (see page 126 in the book Pospelov DA Logical methods of analysis and synthesis of circuits. - M .: Energy, 1974).

The above information allows us to conclude that the proposed logic module, using constant tuning, implements any of five simple symmetric Boolean functions depending on five arguments - input binary signals, and has lower hardware costs and fewer tuning inputs compared to the prototype.

Claims (1)

A logic module designed to implement any of five simple symmetric Boolean functions, depending on five arguments - input binary signals, containing four AND elements, four OR elements and four majority elements, with the first inputs of the third, fourth OR elements and the first, second inputs i th

And element are connected respectively to the outputs of the first OR element, And element, and the first, second inputs of the i-th OR element, the second input and output of the fourth majority element are connected respectively to the output of the third majority element and the output of the logic module, the first, second and third, fourth information the inputs of which are connected respectively to the first, second inputs of the first and first, second inputs of the second elements OR, characterized in that the third inputs of the first, second and second input of the third majority elements connected respectively to the outputs of the second OR element, AND element and the output of the third OR element, the second input and output of the jth

the majority element are connected respectively to the output of the (j + 2) -th AND element and the third input of the (5-j) -th majority element, and the first inputs of the second, fourth majority elements and the combined first inputs of the first, third majority elements are connected respectively to the first, the third and second training inputs of the logic module, the fifth information input of which is connected to the second input of the fourth OR element, connected by the output to the second input of the third element I.

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