RU2641454C2 - Logic converter - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: logic converter contains eight majority elements, each with three inputs. The output of the i-th

and the first inputs of the third, fifth, and sixth majority elements are respectively connected to the second input of the (i+1)-th majority element and the first tuning input of the logic converter, characterized in the fact that the ninth majority element is introduced into it, the output of j-th

and the output of the m-th

majority elements are respectively connected to the second input (j+1)-th and third input (3×m+2)-th majority elements, and the second, third inputs and the output of the ninth majority element are respectively connected to the outputs of the fifth, eighth majority elements and the output of the logic converter, the second and the first tuning inputs of which are respectively connected to the first input of the ninth and the first inputs of the fourth, seventh, eighth majority elements.

EFFECT: extended range of technical means for implementing simple symmetric Boolean functions.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical converters are known (see, for example, RF patent 2281545, class G06F 7/57, 2006), which, using a constant setting, implement any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n depending on n arguments - input binary signals, for n = 4. Moreover, in particular, the aforementioned analogue contains n + 3 majority elements.

The reason that impedes the achievement of the technical result indicated below when using known logic converters is limited functionality, due to the fact that processing of six input signals is not allowed.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2542895, class G06F 7/57, 2015), which contains n + 3 major elements and implements any of simple symmetric Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n , depending on n arguments - input binary signals, for n = 5.

The reason that impedes the achievement of the technical result indicated below when using the prototype is limited functionality due to the fact that six input signals are not allowed to be processed.

The technical result of the invention is the expansion of functionality by providing the implementation using a constant configuration of any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n , depending on n arguments - input binary signals, for n = 6 and hardware composition of n + 3 majority elements.

и первые входы третьего, пятого, шестого мажоритарных элементов соединены соответственно с вторым входом (i+1)-го мажоритарного элемента и первым настроечным входом логического преобразователя, особенность заключается в том, что в него введен девятый мажоритарный элемент, выход j-го

и выход m-го

мажоритарных элементов соединены соответственно с вторым входом (j+1)-го и третьим входом (3×m+2)-го мажоритарных элементов, а второй, третий входы и выход девятого мажоритарного элемента подключены соответственно к выходам пятого, восьмого мажоритарных элементов и выходу логического преобразователя, второй и первый настроечные входы которого соединены соответственно с первым входом девятого и первыми входами четвертого, седьмого, восьмого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logical converter containing eight major elements, which have three inputs, the output of the i-th

and the first inputs of the third, fifth, sixth majority elements are connected respectively to the second input of the (i + 1) -th majority element and the first tuning input of the logic converter, the peculiarity is that the ninth majority element is introduced into it, the output of the jth

and exit m

majority elements are connected respectively to the second input of the (j + 1) -th and third input of the (3 × m + 2) -th majority elements, and the second, third inputs and the output of the ninth majority element are connected respectively to the outputs of the fifth, eighth majority elements and the output logical converter, the second and first tuning inputs of which are connected respectively to the first input of the ninth and first inputs of the fourth, seventh, eighth majority elements.

The drawing shows a diagram of the proposed logical Converter.

, 1_j

и 1_m

соединены соответственно с вторыми входами элементов 1_i+1, 1_j+1 и третьим входом элемента 1_3×m+2, а второй, третий входы и выход элемента 1₉ подключены соответственно к выходам элементов 1₅, 1₈ и выходу логического преобразователя, второй и первый настроечные входы которого соединены соответственно с первыми входами элементов 1₉ и 1_r

.The logical converter contains the majority elements 1 ₁ , ..., 1 ₉ , which have three inputs, and the outputs of the elements 1i

, 1 _j

and 1 _m

connected respectively to the second inputs of the elements 1 _{i + 1} , 1 _{j + 1} and the third input of the element 1 _{3 × m + 2} , and the second, third inputs and the output of the element 1 _{9 are} connected respectively to the outputs of the elements 1 ₅ , 1 ₈ and the output of the logic converter , the second and first tuning inputs of which are connected respectively to the first inputs of elements 1 ₉ and 1 _r

.

,

константной настройки. На первый вход элемента 1₂, второй вход элемента 1₃; второй вход элемента 1₂, третий вход элемента 1₃; третьи входы элементов 1₂, 1₄; первый вход элемента 1₁, второй вход элемента 1₆; второй вход элемента 1₁, третий вход элемента 1₆, третьи входы элементов 1₁, 1₇ подаются соответственно подлежащие обработке двоичные сигналы х₁; х₂; х₃; х₄; х₅; х₆

.The work of the proposed logical Converter is as follows. On its first, second tuning inputs, the necessary signals are fixed accordingly

,

constant settings. At the first input of element 1 ₂ , the second input of element 1 ₃ ; the second input of the element 1 ₂ , the third input of the element 1 ₃ ; third inputs of elements 1 ₂ , 1 ₄ ; the first input of element 1 ₁ , the second input of element 1 ₆ ; the second input of the element 1 ₁ , the third input of the element 1 ₆ , the third inputs of the elements 1 ₁ , 1 ₇ are fed respectively binary signals x ₁ to be processed; x ₂ ; x ₃ ; x ₄ ; x ₅ ; x ₆

.

имеем

, где a_k1, a_k2, a_k3 и

- есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И.At the output of the majority element 1 _k

we have

, where a _k1 , a _k2 , a _k3 and

- there are respectively signals at its first, second, third inputs and symbols of operations OR, I.

Therefore, the signal at the output of element 1 ₉ is determined by the expression:

,

,

wherein

Thus, at the output of the proposed Converter we get:

where τ ₁ , τ ₂ , τ ₅ , τ ₆ are simple symmetric Boolean functions of six arguments x ₁ , ..., x ₆ (see page 126 in the book: D. Pospelov. Logical methods of circuit analysis and synthesis. - M .: Energy, 1974).

The above information allows us to conclude that the proposed logical converter contains n + 3 majority elements and has wider functionality compared to the prototype, since it uses a constant setting to implement any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n , depending on n arguments - input binary signals, for n = 6.

Claims (1)

A logic converter designed to implement simple symmetric Boolean functions, containing eight majority elements that have three inputs, and the i-th output

and the first inputs of the third, fifth, sixth majority elements are connected respectively to the second input of the (i + 1) -th majority element and the first tuning input of the logic converter, characterized in that the ninth majority element is introduced into it, the output of the jth

and exit m

majority elements are connected respectively to the second input of the (j + 1) -th and third input of the (3 × m + 2) -th majority elements, and the second, third inputs and the output of the ninth majority element are connected respectively to the outputs of the fifth, eighth majority elements and the output logical converter, the second and first tuning inputs of which are connected respectively to the first input of the ninth and first inputs of the fourth, seventh, eighth majority elements.

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