RU2629452C1 - Logic converter - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: logic converter is designed to perform simple symmetric Boolean functions and can be used in the digital computer engineering systems like the code conversion means. The method is carried out by using eleven majoritarian elements ₍1₁ …, 1₁₁) and the new circuit of their connection.

EFFECT: ensuring implementation of any of the six simple symmetric Boolean functions depending on six arguments - binary input signals.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logic converters are known (see, for example, RF patent 2443009, class G06F 7/57, 2012), which implement any of five simple symmetric Boolean functions depending on five arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using known logic converters is limited functionality, due to the fact that the implementation of any of the six simple symmetric Boolean functions does not work, depending on six arguments - input binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2393527, class G06F 7/57, 2010), which contains eight major elements and implements any of five simple symmetric Boolean functions, depending on five arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using the prototype is limited functionality, due to the fact that the implementation of any of the six simple symmetric Boolean functions does not work, depending on six arguments - input binary signals.

The technical result of the invention is the expansion of functionality by providing the implementation of any of six simple symmetric Boolean functions, depending on six arguments - input binary signals.

и j-го

мажоритарных элементов соединены соответственно с вторыми входами (i+1)-го и (j+2)-го мажоритарных элементов, выход девятого и выход r-го

мажоритарных элементов подключены соответственно к первому входу третьего и третьему входу (r-3)-го мажоритарных элементов, а третий вход k-го

и выход четвертого мажоритарных элементов соединены соответственно с выходом (k+4)-го мажоритарного элемента и выходом логического преобразователя, четвертый и первый, второй, третий настроечные входы которого подключены соответственно к второму входу одиннадцатого мажоритарного элемента и объединенным первым входам четвертого, пятого мажоритарных элементов, объединенным первым входам восьмого, девятого, одиннадцатого мажоритарных элементов, объединенным первым входам шестого, седьмого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logical converter containing eight majority elements that have three inputs, the first inputs of the first, second majority elements are connected to the first training input of the logical converter, the peculiarity is that it is additionally introduced three majority elements that have three inputs, outputs of the i-th

and j

majority elements are connected respectively to the second inputs of the (i + 1) -th and (j + 2) -th majority elements, the output of the ninth and the output of the r-th

majority elements are connected respectively to the first input of the third and third input of the (r-3) -th majority elements, and the third input of the k-th

and the output of the fourth majority elements are connected respectively to the output of the (k + 4) -th majority element and the output of the logic converter, the fourth and first, second, third tuning inputs of which are connected respectively to the second input of the eleventh majority element and the combined first inputs of the fourth, fifth majority elements , the combined first inputs of the eighth, ninth, eleventh majority elements, the combined first inputs of the sixth, seventh majority elements.

In FIG. The scheme of the proposed logical converter is presented.

и 1_j

соединены соответственно с вторыми входами элементов 1_i+1 и 1_j+2, выход элемента 1₉ и выход элемента 1_r

подключены соответственно к первому входу элемента 1₃ и третьему входу элемента 1_r-3, а третий вход элемента 1_k

и выход элемента 1₄ соединены соответственно с выходом элемента 1_k+4 и выходом логического преобразователя, четвертый и первый, второй, третий настроечные входы которого подключены соответственно к второму входу элемента 1₁₁ и объединенным первым входам элементов 1₁, 1₂, 1₄, 1₅, объединенным первым входам элементов 1₈, 1₉, 1₁₁, объединенным первым входам элементов 1₆, 1₇.The logical converter contains the majority elements 1 ₁ , ..., 1 ₁₁ , which have three inputs, and the outputs of the elements 1 _i

and 1 _j

connected respectively to the second inputs of the elements 1 _{i + 1} and 1 _{j + 2} , the output of the element 1 ₉ and the output of the element 1 _r

connected respectively to the first input of element 1 ₃ and the third input of element 1 _r-3 , and the third input of element 1 _k

and the output of element 1 _{4 are} connected respectively to the output of element 1 _{k + 4} and the output of the logic converter, the fourth and first, second, third tuning inputs of which are connected respectively to the second input of element 1 ₁₁ and the combined first inputs of elements 1 ₁ , 1 ₂ , 1 ₄ , 1 ₅ , the combined first inputs of the elements 1 ₈ , 1 ₉ , 1 ₁₁ , the combined first inputs of the elements 1 ₆ , 1 ₇ .

. На вторые входы элементов 1₁, 1₆, первый вход элемента 1₁₀; третьи входы элементов 1₁, 1₆, второй вход элемента 1₁₀; третьи входы элементов 1₂, 1₁₀, 1₁₁; вторые и третьи входы элементов 1₅, 1₉ подаются соответственно двоичные сигналы х_1; x₂; x₃, x₄ и х₅ (x₁, …, x₅∈{0,1}). На выходе мажоритарного элемента 1_m

имеем Maj(a _m1, a _m2, a _m3)=a _m1 a _m2∨a _m1 a _m3∨a _m2 a _m3, где a _m1, a _m2, a _m3 и ∨; есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И. Следовательно, сигнал на выходе элемента 1₄ определяется выражениемThe work of the proposed logical Converter is as follows. On its first, ..., fourth tuning inputs, the necessary binary signals are supplied accordingly

. To the second inputs of the elements 1 ₁ , 1 ₆ , the first input of the element 1 ₁₀ ; the third inputs of the elements 1 ₁ , 1 ₆ , the second input of the element 1 ₁₀ ; the third inputs of the elements 1 ₂ , 1 ₁₀ , 1 ₁₁ ; the second and third inputs of elements 1 ₅ , 1 ₉ are binary signals x _1, respectively _; x ₂ ; x ₃ , x ₄ and x ₅ (x ₁ , ..., x ₅ ∈ {0,1}). At the output of the majority element 1 _m

we have Maj ( a _m1 , a _m2 , a _m3 ) = a _m1 a _m2 ∨ a _m1 a _m3 ∨ a _m2 a _m3 , where a _m1 , a _m2 , a _m3 and ∨; there are, respectively, signals at its first, second, third inputs and operation symbols OR, I. Therefore, the signal at the output of element 1 ₄ is determined by the expression

где

Where

Thus, at the output of the proposed Converter get

where τ ₁ , ..., τ ₆ are simple symmetric Boolean functions of six arguments x ₁ , ..., x ₆ (see p. 126 in the book Pospelov D.A. Logical methods of analysis and synthesis of circuits. M: Energy, 1974 )

The above information allows us to conclude that the proposed logic converter has wider functionality compared to the prototype, since it implements any of six simple symmetric Boolean functions depending on six arguments - input binary signals.

Claims (1)

A logic converter designed to implement any of six simple symmetric Boolean functions depending on six arguments - input binary signals, containing eight majority elements that have three inputs, the first inputs of the first, second majority elements connected to the first tuning input of the logical converter, characterized in that it additionally introduces three majority elements, which have three inputs, outputs of the i-th

and j

majority elements are connected respectively to the second inputs of the (i + 1) -th and (j + 2) -th majority elements, the output of the ninth and the output of the r-th

majority elements are connected respectively to the first input of the third and third input of the (r-3) -th majority elements, and the third input of the k-th

and the output of the fourth majority elements are connected respectively to the output of the (k + 4) -th majority element and the output of the logic converter, the fourth and first, second, third tuning inputs of which are connected respectively to the second input of the eleventh majority element and the combined first inputs of the fourth, fifth majority elements , the combined first inputs of the eighth, ninth, eleventh majority elements, the combined first inputs of the sixth, seventh majority elements.

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