RU2518669C1 - Logic converter - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device is designed to execute any of four simple symmetric Boolean functions, which depend on four arguments - input binary signals, and can be used in digital computer systems as a code conversion means. The device has five majority elements.

EFFECT: reduced hardware costs.

1 dwg

Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logic converters are known (see, for example, RF patent 2281545, class G06F 7/57, 2006), which contain majority elements and, using a constant setting, implement any of four simple symmetric Boolean functions τ ₁ = x ₁ ∨x ₂ ∨x ₃ ∨x ₄ , τ ₂ = x ₁ x ₂ ∨ x ₁ x ₃ ∨ x ₁ x ₄ ∨ x ₂ x ₃ ∨ x ₂ x ₄ ∨ x ₃ x ₄ , τ ₃ = x ₁ x ₂ x ₃ ∨ x ₁ x ₂ x ₄ ∨x ₁ x ₃ x ₄ ∨x ₂ x ₃ x ₄ , τ ₄ = x ₁ x ₂ x ₃ x ₄ , depending on four arguments - input binary signals x ₁ , x ₂ , x ₃ , x ₄ ∈ {0,1}.

The reason that impedes the achievement of the technical result indicated below when using known logic converters includes high hardware costs, due to the fact that, in particular, the aforementioned analogue contains seven major elements.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2417404, class G06F7 / 57, 2011), which contains the majority elements and implements any of four simple symmetric Boolean constants functions τ ₁ = x ₁ ∨x ₂ ∨x ₃ ∨x ₄ , τ ₂ = x ₁ x ₂ ∨x ₁ x ₃ ∨x ₁ x ₄ ∨x ₂ x ₃ ∨x ₂ x ₄ ∨x ₃ x ₄ , τ ₃ = x ₁ x ₂ x ₃ ∨x ₁ x ₂ x ₄ ∨x ₁ x ₃ x ₄ ∨x ₂ x ₃ x ₄ , τ ₄ = x ₁ x ₂ x ₃ x ₄ , depending on four arguments - binary input signals x ₁ , x ₂ , x ₃ , x ₄ ∈ {0,1}.

The reason that impedes the achievement of the technical result indicated below when using the prototype includes high hardware costs due to the fact that the prototype contains six major elements.

The technical result of the invention is to reduce hardware costs while maintaining the functionality of the prototype.

The specified technical result in the implementation of the invention is achieved by the fact that in a logical converter containing five majority elements and connected by the first, second information inputs respectively to the second, third inputs of the first majority element, the output of which is connected to the second input of the third majority element connected by the first input to the first the input of the fourth majority element and the first tuning input of the logical converter, the feature is that the first, the second and third information inputs of the logical converter are connected respectively to the first, second inputs of the second and the combined third inputs of the second, third majority elements, the fourth information and the first, second tuning inputs of the logical converter are connected respectively to the third input of the fourth and first inputs of the first, fifth majority elements, and the outputs of the second, third, fourth and fifth majority elements are connected respectively to the second inputs of the fourth, fifth, third them fifth input majority logic elements and output transducer.

The drawing shows a diagram of the proposed logical Converter.

и 1₄ соединены соответственно со вторым входом элемента 1_i+2 и третьим входом элемента 1₅, подключенного первым входом и выходом соответственно к второму настроечному входу и выходу логического преобразователя, четвертый информационный вход которого соединен с третьим входом элемента 1₄.The logical converter contains the majority elements 1 ₁ , ..., 1 ₅ , the combined second input of the element 1 ₁ , the first input of the element 1 ₂ , the combined third input of the element 1 ₁ , the second input of the element 1 ₂ , the combined third inputs of the elements 1 ₂ , 1 ₃ the combined first inputs of the elements 1 ₁ , 1 ₃ , 1 ₄ form the first, second, third information and first training inputs of the logic converter, respectively, and the outputs of the elements 1 _i $$\left(i=\overline{1.3}\right)$$

and 1 _{4 are} connected respectively to the second input of element 1 _{i + 2} and the third input of element 1 ₅ connected to the second input and output, respectively, to the second tuning input and output of the logic converter, the fourth information input of which is connected to the third input of element 1 ₄ .

имеем Maj(a _k1, a _k2, a _k3)=ak₁ ak₂∨ak₁ ak₃, где ak₁, ak₂, ak₃ и ∨, • есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И. Следовательно, сигнал на выходе элемента 1₅ определяется выражениемThe work of the proposed logical Converter is as follows. Binary signals x ₁ , ..., x ₄ ∈ {0,1} and signals f ₁ , f ₂ ∈ {0,1} of constant tuning are respectively sent to its first, ..., fourth information and first, second tuning inputs. At the output of the majority element 1 _k $$\left(k=\overline{\mathrm{1,5}}\right)$$

we have Maj ( a _k1 , a _k2 , a _k3 ) = a k ₁ a k ₂ ∨ a k ₁ a k ₃ , where a k ₁ , a k ₂ , a k ₃ and ∨, • there are signals on its first, respectively, second, third inputs and operation symbols OR, I. Therefore, the signal at the output of element 1 ₅ is determined by the expression

$$Z=\left(x_{\mathrm{one}}\stackrel{f_{\mathrm{one}}}{*}{x}_2\stackrel{f_{\mathrm{one}}}{*}{x}_3\right)\stackrel{f_2}{*}\left(x_{\mathrm{four}}\stackrel{f_{\mathrm{one}}}{*}\left(x_{\mathrm{one}}{x}_2\vee x_{\mathrm{one}}{x}_3\vee x_2{x}_3\right)\right),$$

Where

$$\stackrel{f_q}{*}=\{\begin{array}{l}\vee PR\mathrm{and}{f}_q=\mathrm{one}\\ •PR\mathrm{and}{f}_q=0\end{array}\left(q=\overline{\mathrm{1,2}}\right).$$

Thus, at the output of the proposed Converter get

$$Z=\{\begin{array}{l}{x}_{\mathrm{one}}\vee x_2\vee x_3\vee x_{\mathrm{four}}\vee x_{\mathrm{one}}{x}_2\vee x_{\mathrm{one}}{x}_3\vee x_2{x}_3=x_{\mathrm{one}}\vee x_2\vee x_3\vee x_{\mathrm{four}}PR\mathrm{and}{f}_{\mathrm{one}}=f_2=\mathrm{one}\\ \left(x_{\mathrm{one}}\vee x_2\vee x_3\right)\left(x_{\mathrm{four}}\vee x_{\mathrm{one}}{x}_2\vee x_{\mathrm{one}}{x}_3\vee x_2{x}_3\right)=\\ =x_{\mathrm{one}}{x}_2\vee x_{\mathrm{one}}{x}_3\vee x_{\mathrm{one}}{x}_{\mathrm{four}}\vee x_2{x}_3\vee x_2{x}_{\mathrm{four}}\vee x_3{x}_{\mathrm{four}}PR\mathrm{and}{f}_{\mathrm{one}}=\mathrm{one,}{f}_2=0\\ x_{\mathrm{one}}{x}_2{x}_3\vee x_{\mathrm{four}}\left(x_{\mathrm{one}}{x}_2\vee x_{\mathrm{one}}{x}_3\vee x_2{x}_3\right)=\\ =x_{\mathrm{one}}{x}_2{x}_3\vee x_{\mathrm{one}}{x}_2{x}_{\mathrm{four}}\vee x_{\mathrm{one}}{x}_3{x}_{\mathrm{four}}\vee x_2{x}_3{x}_{\mathrm{four}}PR\mathrm{and}{f}_{\mathrm{one}}=0f_2=\mathrm{one}\\ x_{\mathrm{one}}{x}_2{x}_3{x}_{\mathrm{four}}\left(x_{\mathrm{one}}{x}_2\vee x_{\mathrm{one}}{x}_3\vee x_2{x}_3\right)=x_{\mathrm{one}}{x}_2{x}_3{x}_{\mathrm{four}}PR\mathrm{and}{f}_{\mathrm{one}}=f_2=0\end{array}$$

The above information allows us to conclude that the proposed logical converter using constant settings implements any of the four simple symmetric Boolean functions τ ₁ = x ₁ ∨x ₂ ∨x ₃ ∨x ₄ , τ ₂ = x ₁ x ₂ ∨x ₁ x ₃ ∨ x ₁ x ₄ ∨x ₂ x ₃ ∨x ₂ x ₄ ∨x ₃ x ₄ , τ ₃ = x ₁ x ₂ x ₃ ∨x ₁ x ₂ x ₄ ∨x ₁ x ₃ x ₄ ∨x ₂ x ₃ x ₄ , τ ₄ = x ₁ x ₂ x ₃ x ₄ , depending on four arguments - input binary signals x ₁ , x ₂ , x ₃ , x ₄ ∈ {0,1}, and has lower hardware costs compared to the prototype, since contains one majority element less than in the hardware composition of the prototype.

Claims (1)

A logic converter designed to implement any of four simple symmetric Boolean functions, depending on four arguments - input binary signals, containing five majority elements and connected by the first, second information inputs respectively to the second, third inputs of the first majority element, the output of which is connected to the second input the third majority element connected by the first input to the first input of the fourth majority element and the first tuning input of the logical about the converter, characterized in that the first, second and third information inputs of the logical converter are connected respectively to the first, second inputs of the second and the combined third inputs of the second, third majority elements, the fourth information and the first, second tuning inputs of the logical converter are connected respectively to the third input of the fourth and the first inputs of the first, fifth majority elements, and the outputs of the second, third, fourth and fifth majority elements are connected respectively enno to second inputs of the fourth, fifth, fifth third input majority logic elements and output transducer.