[go: up one dir, main page]

NL8803213A - Werkwijze voor het vervaardigen van een snelle cmos ttl halfgeleiderinrichting. - Google Patents

Werkwijze voor het vervaardigen van een snelle cmos ttl halfgeleiderinrichting. Download PDF

Info

Publication number
NL8803213A
NL8803213A NL8803213A NL8803213A NL8803213A NL 8803213 A NL8803213 A NL 8803213A NL 8803213 A NL8803213 A NL 8803213A NL 8803213 A NL8803213 A NL 8803213A NL 8803213 A NL8803213 A NL 8803213A
Authority
NL
Netherlands
Prior art keywords
zone
oxide layer
forming
substrate
layer
Prior art date
Application number
NL8803213A
Other languages
English (en)
Dutch (nl)
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of NL8803213A publication Critical patent/NL8803213A/nl

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/858—Complementary IGFETs, e.g. CMOS comprising a P-type well but not an N-type well

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
NL8803213A 1987-12-31 1988-12-30 Werkwijze voor het vervaardigen van een snelle cmos ttl halfgeleiderinrichting. NL8803213A (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR870015551 1987-12-31
KR1019870015551A KR900005354B1 (ko) 1987-12-31 1987-12-31 Hct 반도체 장치의 제조방법

Publications (1)

Publication Number Publication Date
NL8803213A true NL8803213A (nl) 1989-07-17

Family

ID=19267824

Family Applications (1)

Application Number Title Priority Date Filing Date
NL8803213A NL8803213A (nl) 1987-12-31 1988-12-30 Werkwijze voor het vervaardigen van een snelle cmos ttl halfgeleiderinrichting.

Country Status (7)

Country Link
US (1) US4920066A (ja)
JP (1) JPH023270A (ja)
KR (1) KR900005354B1 (ja)
DE (1) DE3843103A1 (ja)
FR (1) FR2625609B1 (ja)
GB (1) GB2213321B (ja)
NL (1) NL8803213A (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3924062C2 (de) * 1989-07-21 1993-11-25 Eurosil Electronic Gmbh EEPROM-Halbleitereinrichtung mit Isolierzonen für Niedervolt-Logikelemente
EP0488801B1 (en) * 1990-11-30 1998-02-04 Sharp Kabushiki Kaisha Thin-film semiconductor device
US5438005A (en) * 1994-04-13 1995-08-01 Winbond Electronics Corp. Deep collection guard ring
US6017785A (en) * 1996-08-15 2000-01-25 Integrated Device Technology, Inc. Method for improving latch-up immunity and interwell isolation in a semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983620A (en) * 1975-05-08 1976-10-05 National Semiconductor Corporation Self-aligned CMOS process for bulk silicon and insulating substrate device
US4152823A (en) * 1975-06-10 1979-05-08 Micro Power Systems High temperature refractory metal contact assembly and multiple layer interconnect structure
JPS5543842A (en) * 1978-09-25 1980-03-27 Hitachi Ltd Manufacture of al gate cmos ic
JPS5565446A (en) * 1978-11-10 1980-05-16 Nec Corp Semiconductor device
US4288910A (en) * 1979-04-16 1981-09-15 Teletype Corporation Method of manufacturing a semiconductor device
DE3133841A1 (de) * 1981-08-27 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
DE3318213A1 (de) * 1983-05-19 1984-11-22 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum herstellen eines integrierten isolierschicht-feldeffekttransistors mit zur gateelektrode selbstausgerichteten kontakten

Also Published As

Publication number Publication date
GB8900015D0 (en) 1989-03-01
KR890011084A (ko) 1989-08-12
GB2213321A (en) 1989-08-09
FR2625609A1 (fr) 1989-07-07
FR2625609B1 (fr) 1992-07-03
KR900005354B1 (ko) 1990-07-27
JPH023270A (ja) 1990-01-08
US4920066A (en) 1990-04-24
DE3843103A1 (de) 1989-07-13
GB2213321B (en) 1991-03-27

Similar Documents

Publication Publication Date Title
JP2510751B2 (ja) 単一集積回路チップ上に高電圧及び低電圧ｃｍｏｓトランジスタを形成するためのプロセス
US5444008A (en) High-performance punchthrough implant method for MOS/VLSI
NL8802219A (nl) Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin door ionenimplantaties halfgeleidergebieden worden gevormd.
US4933994A (en) Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide
EP0482232B1 (de) Verfahren zur Herstellung einer dotierten Polyzidschicht auf einem Halbleitersubstrat
US5925914A (en) Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance
DE69938381T2 (de) Herstellung einer LDD Struktur für eine Schutzschaltung gegen elektrostatische Entladungen (ESD)
EP0072967B1 (de) Verfahren zum Herstellen von hochintegrierten komplementären MOS-Feldeffekttransistorschaltungen in Siliziumgate-Technologie
US5030582A (en) Method of fabricating a CMOS semiconductor device
KR940001436A (ko) 티탄늄 실리사이드(titanium sillicide) 콘택 제조방법
EP0159617B1 (de) Verfahren zum Herstellen von hochintegrierten MOS-Feldeffekttransistoren
US5288653A (en) Process of fabricating an insulated-gate field effect transistor
KR970018223A (ko) 반도체 집적 회로의 제조 방법
NL8803213A (nl) Werkwijze voor het vervaardigen van een snelle cmos ttl halfgeleiderinrichting.
US5273914A (en) Method of fabricating a CMOS semiconductor devices
US5780347A (en) Method of forming polysilicon local interconnects
US5266508A (en) Process for manufacturing semiconductor device
US5486482A (en) Process for fabricating metal-gate CMOS transistor
JPH02264464A (ja) 半導体装置およびその製造方法
JPH04218925A (ja) 半導体装置およびその製造方法
US5739058A (en) Method to control threshold voltage by modifying implant dosage using variable aperture dopant implants
JPH0587191B2 (ja)
DE4319437C1 (de) Verfahren zur Herstellung einer monolithisch integrierten Schaltung mit mindestens einem CMOS-Feldeffekttransistor und einem npn-Bipolar-Transistor
KR19990035801A (ko) 자기 조절 콘택 및 도핑 영역의 제조 방법
JP2860483B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A1A A request for search or an international-type search has been filed
BB A search report has been drawn up
BC A request for examination has been filed
BV The patent application has lapsed