KR970067910A - 실리콘 온 인슐레이터(soi)구조를 갖는 입력/출력 보호회로 - Google Patents
실리콘 온 인슐레이터(soi)구조를 갖는 입력/출력 보호회로 Download PDFInfo
- Publication number
- KR970067910A KR970067910A KR1019970000189A KR19970000189A KR970067910A KR 970067910 A KR970067910 A KR 970067910A KR 1019970000189 A KR1019970000189 A KR 1019970000189A KR 19970000189 A KR19970000189 A KR 19970000189A KR 970067910 A KR970067910 A KR 970067910A
- Authority
- KR
- South Korea
- Prior art keywords
- input
- protection circuit
- semiconductor film
- output protection
- insulating layer
- Prior art date
Links
- 239000012212 insulator Substances 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims 8
- 238000000034 method Methods 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (3)
- 입력/출력단자(30)와 복수의 MOS트랜지스터(44,45)를 포함하는 내부회로(31)와의 사이에 접속되고 절연층(2)상에 형성되는 입력/출력보호회로에 있어서 상기 절연층상에 형성되고 상기 입력/출력단자와 제1 전원선(32)와의 사이에 접속된 제1 반도체막(3)과 상기 제1 반도체막상에 형성된 제1 게이트 절연막(34d,38d,34g)과 상기 제1 게이트 절연막상에 형성되고 플로팅 상태에 있는 제1 게이트 전극(34a,38a,34f)을 구비한 제1 MOS소자(34,38)를 포함하는 입력/출력보호회로.
- 입력/출력단자(30)와 복수의 MOS트랜지스터(44,45)를 포함하는 내부회로와의 사이에 접속되고 절연층상에 형성되는 입력/출력보호회로에 상기 복수의 MOS트랜지스터가 서로 필드 실드법에 의해 분리되어 있는 상기 입력/출력보호회로에 있어서 상기 절연층상에 형성되고 상기 입력/출력단자와 전원선(32,33)과의 사이에 접속된 반도체막(3)과 상기 반도체막상에 형성된 게이트 절연막(34g,35g)과 상기 게이트 절연막상에서상기 플드 실드법에 의한 분리용의 게이트 전극(16)과 동일한 층에 형성된 게이트 전극(34f,35f)을 구비한 MOS소자를 포함하는 입력/출력보호회로.
- 입력/출력단자(30)와 내부회로(31)와의 사이에 접속되고 절연층(2)상에 형성되는 입력/출력보호회로에 있어서 상기 절연층상에 형성된 제1 도전형의 반도체막(3)과 상기 반도체막내에 형성되고 상기 입력/출력단자에 접속된 제1도전형의 복수의 제1도전 영역(62,61)과 상기 반도체막내에 형성되고 전원선(32,33)에 접속된 제2도전형의 복수의 제2 도전 영역(61,62)을 포함하는 입력/출력보호회로.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9676305 | 1996-03-29 | ||
JP07630596A JP3717227B2 (ja) | 1996-03-29 | 1996-03-29 | 入力/出力保護回路 |
JP96-76305 | 1996-03-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970067910A true KR970067910A (ko) | 1997-10-13 |
KR100294412B1 KR100294412B1 (ko) | 2001-07-12 |
Family
ID=13601670
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970000189A KR100294412B1 (ko) | 1996-03-29 | 1997-01-07 | 실리콘온인슐레이터(soi)구조를갖는입/출력보호회로 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6118154A (ko) |
JP (1) | JP3717227B2 (ko) |
KR (1) | KR100294412B1 (ko) |
DE (1) | DE19651247C2 (ko) |
FR (1) | FR2746963B1 (ko) |
TW (1) | TW312052B (ko) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4054093B2 (ja) | 1997-10-09 | 2008-02-27 | 株式会社ルネサステクノロジ | 半導体装置 |
US6521947B1 (en) | 1999-01-28 | 2003-02-18 | International Business Machines Corporation | Method of integrating substrate contact on SOI wafers with STI process |
FR2789226B1 (fr) * | 1999-01-29 | 2002-06-14 | Commissariat Energie Atomique | Dispositif de protection contre les decharges electrostatiques pour composants microelectroniques sur substrat du type soi |
JP3851738B2 (ja) * | 1999-01-29 | 2006-11-29 | 株式会社東芝 | 半導体装置 |
JP3988914B2 (ja) * | 1999-04-28 | 2007-10-10 | 株式会社ルネサステクノロジ | 静電破壊保護回路を有する半導体集積回路 |
US6587320B1 (en) * | 2000-01-04 | 2003-07-01 | Sarnoff Corporation | Apparatus for current ballasting ESD sensitive devices |
DE10022367C2 (de) * | 2000-05-08 | 2002-05-08 | Micronas Gmbh | ESD-Schutzstruktur und Verfahren zur Herstellung |
US6583972B2 (en) | 2000-06-15 | 2003-06-24 | Sarnoff Corporation | Multi-finger current ballasting ESD protection circuit and interleaved ballasting for ESD-sensitive circuits |
TW587345B (en) * | 2003-02-21 | 2004-05-11 | Toppoly Optoelectronics Corp | Method and structure of diode |
JP2005156703A (ja) * | 2003-11-21 | 2005-06-16 | Seiko Epson Corp | 電子装置の静電保護回路、電気光学装置の静電保護回路及び電子機器 |
JP2006032543A (ja) * | 2004-07-14 | 2006-02-02 | Seiko Instruments Inc | 半導体集積回路装置 |
JP2006060191A (ja) * | 2004-07-23 | 2006-03-02 | Seiko Epson Corp | 薄膜半導体装置及びその製造方法、電気光学装置、電子機器 |
US7365610B2 (en) * | 2005-03-21 | 2008-04-29 | Silicon Laboratories Inc. | Push compensation in an oscillator |
JP2006294719A (ja) * | 2005-04-07 | 2006-10-26 | Oki Electric Ind Co Ltd | 半導体装置 |
JP2007212711A (ja) * | 2006-02-09 | 2007-08-23 | Epson Imaging Devices Corp | 保護回路、半導体回路基板、電気光学装置の駆動回路、電気光学装置及び電子機器 |
JP4993941B2 (ja) * | 2006-04-27 | 2012-08-08 | パナソニック株式会社 | 半導体集積回路及びこれを備えたシステムlsi |
DE102006022105B4 (de) * | 2006-05-11 | 2012-03-08 | Infineon Technologies Ag | ESD-Schutz-Element und ESD-Schutz-Einrichtung zur Verwendung in einem elektrischen Schaltkreis |
JP4803747B2 (ja) * | 2007-06-18 | 2011-10-26 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
JP5448584B2 (ja) * | 2008-06-25 | 2014-03-19 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US8174047B2 (en) * | 2008-07-10 | 2012-05-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
DE102008047850B4 (de) | 2008-09-18 | 2015-08-20 | Austriamicrosystems Ag | Halbleiterkörper mit einer Schutzstruktur und Verfahren zum Herstellen derselben |
US9019666B2 (en) | 2010-01-22 | 2015-04-28 | Stmicroelectronics S.A. | Electronic device, in particular for protection against electrostatic discharges, and method for protecting a component against electrostatic discharges |
US9614367B2 (en) | 2013-09-13 | 2017-04-04 | Stmicroelectronics Sa | Electronic device for ESD protection |
US10204791B1 (en) * | 2017-09-22 | 2019-02-12 | Power Integrations, Inc. | Contact plug for high-voltage devices |
JP7631320B2 (ja) * | 2020-04-08 | 2025-02-18 | ローム株式会社 | 半導体装置 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3555374A (en) * | 1967-03-03 | 1971-01-12 | Hitachi Ltd | Field effect semiconductor device having a protective diode |
US4282556A (en) * | 1979-05-21 | 1981-08-04 | Rca Corporation | Input protection device for insulated gate field effect transistor |
US4745450A (en) * | 1984-03-02 | 1988-05-17 | Zilog, Inc. | Integrated circuit high voltage protection |
JPS61133655A (ja) * | 1984-12-03 | 1986-06-20 | Mitsubishi Electric Corp | Mos形半導体集積回路装置 |
JPS6271275A (ja) * | 1985-09-25 | 1987-04-01 | Toshiba Corp | 半導体集積回路 |
US4989057A (en) * | 1988-05-26 | 1991-01-29 | Texas Instruments Incorporated | ESD protection for SOI circuits |
US4875130A (en) * | 1988-07-06 | 1989-10-17 | National Semiconductor Corporation | ESD low resistance input structure |
JP2644342B2 (ja) * | 1989-09-01 | 1997-08-25 | 東芝マイクロエレクトロニクス株式会社 | 入力保護回路を備えた半導体装置 |
JP3128813B2 (ja) * | 1990-08-24 | 2001-01-29 | 日本電気株式会社 | 半導体集積回路 |
JPH04233758A (ja) * | 1990-12-28 | 1992-08-21 | Ricoh Co Ltd | 半導体装置とその製造方法 |
JPH04365373A (ja) * | 1991-06-13 | 1992-12-17 | Nec Corp | 半導体集積回路装置 |
JP3247801B2 (ja) * | 1993-07-27 | 2002-01-21 | 三菱電機株式会社 | Soi構造を有する半導体装置およびその製造方法 |
DE4341170C2 (de) * | 1993-12-02 | 2001-05-03 | Siemens Ag | ESD-Schutzstruktur für integrierte Schaltungen |
JP3447372B2 (ja) * | 1994-06-13 | 2003-09-16 | 富士通株式会社 | 半導体装置 |
US5510728A (en) * | 1994-07-14 | 1996-04-23 | Vlsi Technology, Inc. | Multi-finger input buffer with transistor gates capacitively coupled to ground |
JPH0837284A (ja) * | 1994-07-21 | 1996-02-06 | Nippondenso Co Ltd | 半導体集積回路装置 |
JPH0923017A (ja) * | 1995-07-06 | 1997-01-21 | Mitsubishi Electric Corp | Soi入力保護回路 |
-
1996
- 1996-03-29 JP JP07630596A patent/JP3717227B2/ja not_active Expired - Fee Related
- 1996-10-29 TW TW085113209A patent/TW312052B/zh not_active IP Right Cessation
- 1996-12-10 FR FR9615155A patent/FR2746963B1/fr not_active Expired - Fee Related
- 1996-12-10 DE DE19651247A patent/DE19651247C2/de not_active Expired - Fee Related
-
1997
- 1997-01-07 KR KR1019970000189A patent/KR100294412B1/ko not_active IP Right Cessation
- 1997-10-08 US US08/947,345 patent/US6118154A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR100294412B1 (ko) | 2001-07-12 |
JPH09270492A (ja) | 1997-10-14 |
FR2746963B1 (fr) | 2001-01-05 |
TW312052B (en) | 1997-08-01 |
JP3717227B2 (ja) | 2005-11-16 |
DE19651247A1 (de) | 1997-10-02 |
FR2746963A1 (fr) | 1997-10-03 |
DE19651247C2 (de) | 2002-01-10 |
US6118154A (en) | 2000-09-12 |
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