KR950700592A - 한 비트를 래칭하기 위한 회로와 이를 어드레스 래치로 이용하는 방법(circuit for the buffer storage of a bit, and use of the circuit as an address buffer store) - Google Patents

한 비트를 래칭하기 위한 회로와 이를 어드레스 래치로 이용하는 방법(circuit for the buffer storage of a bit, and use of the circuit as an address buffer store)

Info

Publication number: KR950700592A
Authority: KR; South Korea
Prior art keywords: circuit; bit; address; latching; storage element
Prior art date: 1992-02-21

Application number

KR1019940702870A

Other languages

English (en)

Other versions

KR100255701B1 (ko

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1992-02-21

Filing date

1994-08-19

Publication date

1995-01-16

1993-02-01 Application filed filed Critical

1995-01-16 Publication of KR950700592A publication Critical patent/KR950700592A/ko

2000-05-01 Application granted granted Critical

2000-05-01 Publication of KR100255701B1 publication Critical patent/KR100255701B1/ko

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Computer Hardware Design (AREA)
Dram (AREA)
Static Random-Access Memory (AREA)
Communication Control (AREA)
Transceivers (AREA)
Logic Circuits (AREA)

KR1019940702870A 1992-02-21 1993-02-01 한 비트를 래칭하기 위한 회로와 이를 어드레스 래치로 이용하는 방법 KR100255701B1 (ko)

Applications Claiming Priority (3)

Application Number	Priority Date	Filing Date	Title
DE4205339		1992-02-21
DEP4205339.0		1992-02-21
PCT/DE1993/000076 WO1993017434A1 (de)	1992-02-21	1993-02-01	Schaltungsanordnung zum zwischenspeichern eines bits und deren verwendung als adresszwischenspeicher

Publications (2)

Publication Number	Publication Date
KR950700592A true KR950700592A (ko)	1995-01-16
KR100255701B1 KR100255701B1 (ko)	2000-05-01

Family

ID=6452285

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
KR1019940702870A KR100255701B1 (ko)	1992-02-21	1993-02-01	한 비트를 래칭하기 위한 회로와 이를 어드레스 래치로 이용하는 방법

Country Status (9)

Country	Link
US (1)	US5448194A (ko)
EP (1)	EP0627117B1 (ko)
JP (1)	JP3522751B2 (ko)
KR (1)	KR100255701B1 (ko)
AT (1)	ATE128572T1 (ko)
DE (1)	DE59300689D1 (ko)
HK (1)	HK1001178A1 (ko)
TW (1)	TW294861B (ko)
WO (1)	WO1993017434A1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US7094427B2 (en) *	2002-05-29	2006-08-22	Impax Laboratories, Inc.	Combination immediate release controlled release levodopa/carbidopa dosage forms

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4156940A (en) *	1978-03-27	1979-05-29	Rca Corporation	Memory array with bias voltage generator
US4754165A (en) *	1986-07-29	1988-06-28	Hewlett-Packard Company	Static MOS super buffer latch
EP0262411A1 (de) *	1986-09-01	1988-04-06	Siemens Aktiengesellschaft	Adressdecoder für CMOS-Schaltkreise
EP0361807A3 (en) *	1988-09-30	1990-10-17	Advanced Micro Devices, Inc.	Shift register bit apparatus
JPH02141993A (ja) *	1988-11-21	1990-05-31	Toshiba Corp	半導体記憶装置
US5003513A (en) *	1990-04-23	1991-03-26	Motorola, Inc.	Latching input buffer for an ATD memory
US5347173A (en) *	1990-07-31	1994-09-13	Texas Instruments Incorporated	Dynamic memory, a power up detection circuit, and a level detection circuit
US5128897A (en) *	1990-09-26	1992-07-07	Sgs-Thomson Microelectronics, Inc.	Semiconductor memory having improved latched repeaters for memory row line selection
EP0505653A1 (en) *	1991-03-29	1992-09-30	International Business Machines Corporation	Combined sense amplifier and latching circuit for high speed ROMs
US5349243A (en) *	1993-06-30	1994-09-20	Sgs-Thomson Microelectronics, Inc.	Latch controlled output driver
US5396108A (en) *	1993-09-30	1995-03-07	Sgs-Thomson Microelectronics, Inc.	Latch controlled output driver

1993
- 1993-01-15 TW TW082100226A patent/TW294861B/zh not_active IP Right Cessation
- 1993-02-01 EP EP93902065A patent/EP0627117B1/de not_active Expired - Lifetime
- 1993-02-01 DE DE59300689T patent/DE59300689D1/de not_active Expired - Lifetime
- 1993-02-01 KR KR1019940702870A patent/KR100255701B1/ko not_active IP Right Cessation
- 1993-02-01 JP JP51442993A patent/JP3522751B2/ja not_active Expired - Fee Related
- 1993-02-01 AT AT93902065T patent/ATE128572T1/de not_active IP Right Cessation
- 1993-02-01 WO PCT/DE1993/000076 patent/WO1993017434A1/de active IP Right Grant
1994
- 1994-08-17 US US08/290,801 patent/US5448194A/en not_active Expired - Lifetime
1998
- 1998-01-12 HK HK98100229A patent/HK1001178A1/xx not_active IP Right Cessation

Also Published As

Publication number	Publication date
JPH07504289A (ja)	1995-05-11
JP3522751B2 (ja)	2004-04-26
DE59300689D1 (de)	1995-11-02
EP0627117A1 (de)	1994-12-07
TW294861B (ko)	1997-01-01
EP0627117B1 (de)	1995-09-27
WO1993017434A1 (de)	1993-09-02
US5448194A (en)	1995-09-05
ATE128572T1 (de)	1995-10-15
HK1001178A1 (en)	1998-05-29
KR100255701B1 (ko)	2000-05-01

Publication	Publication Date	Title
KR920001539A (ko)	1992-01-30	적분 논리 기능을 가진 감지증폭기
JPS5619586A (en)	1981-02-24	Semiconductor memory unit
KR900008526A (ko)	1990-06-04	반도체 기억장치
KR960018901A (ko)	1996-06-17	피이드백 래치 및 피이드백 래치의 피이드백 동작 형성 방법
KR870002653A (ko)	1987-04-06	래치 엎 현상을 감소시키는 상보형 반도체장치
KR940012618A (ko)	1994-06-24	반도체 집적회로장치
KR920022293A (ko)	1992-12-19	비정기적인 리프레쉬 동작을 실행하는 반도체 메모리 장치
US5901110A (en)	1999-05-04	Synchronous memory with dual sensing output path each of which is connected to latch circuit
KR950703784A (ko)	1995-09-20	잡음 감소형 고속 메모리 감지 증폭기(high speed memory sense amplifier with noise reduction)
KR960038997A (ko)	1996-11-21	반도체 메모리장치의 전류센스앰프회로
KR950020704A (ko)	1995-07-24	반도체 메모리 장치
KR950004271A (ko)	1995-02-17	반도체 메모리 장치의 전원전압 감지회로
KR950700592A (ko)	1995-01-16	한 비트를 래칭하기 위한 회로와 이를 어드레스 래치로 이용하는 방법(circuit for the buffer storage of a bit, and use of the circuit as an address buffer store)
KR950006300B1 (ko)	1995-06-13	반도체 메모리 회로
ATE61173T1 (de)	1991-03-15	Verriegelungsschaltung mit dynamisch waehlbarer polaritaet des ausgangs.
KR950015394A (ko)	1995-06-16	스태틱 랜덤 억세스 메모리
KR850008238A (ko)	1985-12-13	반도체 기억장치
KR870007511A (ko)	1987-08-19	데이타 판독회로
KR920007187A (ko)	1992-04-28	반도체 기억장치
KR950004856B1 (en)	1995-05-15	Data transmitiing circuit
JP2563570B2 (ja)	1996-12-11	セット・リセット式フリップフロップ回路
KR960042746A (ko)	1996-12-21	반도체 메모리장치의 다이나믹 레벨 컨버터
KR900010778A (ko)	1990-07-09	반도체 메모리장치
US6822885B2 (en)	2004-11-23	High speed latch and compare function
KR0182011B1 (ko)	1999-04-15	출력 데이타 안정화를 위한 라이트 드라이버

Legal Events

Date	Code	Title	Description
1994-08-19	PA0105	International application	Patent event date: 19940819 Patent event code: PA01051R01D Comment text: International Patent Application
1995-01-16	PG1501	Laying open of application
1997-08-26	A201	Request for examination
1997-08-26	PA0201	Request for examination	Patent event code: PA02012R01D Patent event date: 19970826 Comment text: Request for Examination of Application
1999-11-30	E701	Decision to grant or registration of patent right
1999-11-30	PE0701	Decision of registration	Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19991130
2000-02-16	GRNT	Written decision to grant
2000-02-16	PR0701	Registration of establishment	Comment text: Registration of Establishment Patent event date: 20000216 Patent event code: PR07011E01D
2000-02-16	PR1002	Payment of registration fee	Payment date: 20000217 End annual number: 3 Start annual number: 1
2000-05-01	PG1601	Publication of registration
2003-01-23	PR1001	Payment of annual fee	Payment date: 20030124 Start annual number: 4 End annual number: 4
2004-01-29	PR1001	Payment of annual fee	Payment date: 20040130 Start annual number: 5 End annual number: 5
2005-01-27	PR1001	Payment of annual fee	Payment date: 20050128 Start annual number: 6 End annual number: 6
2006-01-31	PR1001	Payment of annual fee	Payment date: 20060201 Start annual number: 7 End annual number: 7
2007-01-25	PR1001	Payment of annual fee	Payment date: 20070126 Start annual number: 8 End annual number: 8
2008-01-25	FPAY	Annual fee payment	Payment date: 20080128 Year of fee payment: 9
2008-01-25	PR1001	Payment of annual fee	Payment date: 20080128 Start annual number: 9 End annual number: 9
2009-02-17	LAPS	Lapse due to unpaid annual fee
2009-02-17	PC1903	Unpaid annual fee	Termination category: Default of registration fee Termination date: 20100109