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KR950007086A - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR950007086A
KR950007086A KR1019940019584A KR19940019584A KR950007086A KR 950007086 A KR950007086 A KR 950007086A KR 1019940019584 A KR1019940019584 A KR 1019940019584A KR 19940019584 A KR19940019584 A KR 19940019584A KR 950007086 A KR950007086 A KR 950007086A
Authority
KR
South Korea
Prior art keywords
power supply
well
circuit
substrate
wells
Prior art date
Application number
KR1019940019584A
Other languages
English (en)
Other versions
KR0139701B1 (ko
Inventor
마사요시 오노
Original Assignee
사토 후미오
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 사토 후미오, 가부시키가이샤 도시바 filed Critical 사토 후미오
Publication of KR950007086A publication Critical patent/KR950007086A/ko
Application granted granted Critical
Publication of KR0139701B1 publication Critical patent/KR0139701B1/ko

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • H10D89/213—Design considerations for internal polarisation in field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명의 동일기판판상에 형성되고, 전원계통을 다르게 한 복수의 회로를 갖춘 반도체장치에 있어서, 전원간의 간섭이 적은 ESD보호회로를 제공한다.
본 발명에 구성으로는, 서로 전기적으로 분리된 적어도 제1 및 제2웰이 형성된 반도체기판과, 상기 제1웰내에 형성되면서 제1회로전원에 전원단자를 매개로 접속된 제1전리회로, 상기 제2웰내에 형성되면서 제2회로전원에 전원단자를 매개로 접속된 제2전기회로, 상기 반도체기판상에 형성되면서 안정한 기준전위를 부여하는 제3회로 전원에 접속된 기판접지용 웰, 상기 제1전원의 전원단자와 상기 기판접지웰간에 역바이어스되도록 접속된 제1보호다이오드 및, 상기 제2전원의 전원단자와 상기 기판접지웰간에 역바이어스되도록 접속된 제2보호다이오드를 구비한다.
또한, 본 발명에 의하면 다른 쪽의 전기회로인 아날로그회로의 전원이 ESD보호회로의 다이오드용량을 매개로 디지털회로계의 간섭을 받기 어려운 구조가 얻어진다.

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예를 나타낸 블록회로도.
제2도는 제1실시예의 반도체장치의 구조를 나타낸 단면도.
제3도는 제1실시예의 반도체장치를 역극성의 불순물층에 의해 형성한 예를 나타낸 단면도.

Claims (4)

  1. 서로 전기적으로 분리된 적어도 제1 및 제2웰(5a,5b)이 형성된 반도체기판(3)과, 상기 제1웰(5a)내에 형성되면서 제1회로전원에 전원단자를 매개로 접속된 제1전기호로(1), 상기 제2웰(5b)내에 형성되면서 제2회로전원에 전원단자를 매개로 접속된 제2전기회로(2), 상기 반도체기판(3)에 형성되면서 안정된 기준전위를 부여하는 제3회로전원에 접속된 기판접지용 웰(4), 상기 제1전원의 전원단자와 상기 기판접지웰간에 역바이어스되도록 접속된 제1보호다이오드(d1,d3) 및, 상기 제2전원의 전원단자와 상기 기판접지웰간에 역바이어스되도록 접속된 제2보호다이오드(d2,d4)를 구비하여 구성된 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 제1 및 제2웰(5a,5b)이 상기 반도체기판(3)에 깊게 형성된 딥웰내에 형성된 P웰 및 N웰(6a,6b;7a,7b)을 포함한 트리플웰 구조에 의해 전기적으로 분리된 것을 특징으로 하는 반도제장치.
  3. 제1항에 있어서, 상기 보호다이오드(d1,d2)가 다이오드(d3,d4)와 다이오드접속된 바이폴라 트랜지스터(Tr1,Tr2) 및 다이오드접속된 MOS 트랜지스터(M1,M2)중 어느 하나 또는 이를 조합시킨 것을 특징으로 하는 반도제장치.
  4. 제1항 내지 제3항에 있어서, 상기 제1 및 제2웰(5a,5b), 딥웰 혹은 기판접지용 웰(4)중 적어도 1개가 에피택셜성장에 의해 형성된 것을 특징으로 하는 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940019584A 1993-08-09 1994-08-09 반도체장치 KR0139701B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP19735093A JP3210147B2 (ja) 1993-08-09 1993-08-09 半導体装置
JP93-197350 1993-08-09

Publications (2)

Publication Number Publication Date
KR950007086A true KR950007086A (ko) 1995-03-21
KR0139701B1 KR0139701B1 (ko) 1998-06-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940019584A KR0139701B1 (ko) 1993-08-09 1994-08-09 반도체장치

Country Status (3)

Country Link
US (1) US5796147A (ko)
JP (1) JP3210147B2 (ko)
KR (1) KR0139701B1 (ko)

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JP2943738B2 (ja) * 1996-11-29 1999-08-30 日本電気株式会社 半導体装置における静電保護回路
US6137143A (en) * 1998-06-30 2000-10-24 Intel Corporation Diode and transistor design for high speed I/O
JP2001094050A (ja) 1999-09-21 2001-04-06 Mitsubishi Electric Corp 半導体装置
KR100308086B1 (ko) * 1999-11-01 2001-11-02 박종섭 반도체 소자의 제조방법
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JP4312451B2 (ja) * 2002-12-24 2009-08-12 Ｎｅｃエレクトロニクス株式会社 静電気保護素子及び半導体装置
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FR2853487A1 (fr) * 2003-04-01 2004-10-08 St Microelectronics Sa Composant electronique permettant le decodage de signaux de television numerique par satellite
FR2853486B1 (fr) * 2003-04-03 2005-08-05 St Microelectronics Sa Composant electronique permettant le decodage de signaux de television numerique ou par cable
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JP4447415B2 (ja) 2004-09-22 2010-04-07 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4755405B2 (ja) 2004-10-13 2011-08-24 ルネサスエレクトロニクス株式会社 半導体装置
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JP4993941B2 (ja) * 2006-04-27 2012-08-08 パナソニック株式会社 半導体集積回路及びこれを備えたシステムｌｓｉ
JP5122248B2 (ja) 2007-11-15 2013-01-16 オンセミコンダクター・トレーディング・リミテッド 半導体集積回路
JP4803756B2 (ja) * 2008-02-18 2011-10-26 ルネサスエレクトロニクス株式会社 半導体集積回路装置
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JP2011166153A (ja) * 2010-02-12 2011-08-25 Samsung Electronics Co Ltd ガードリング構造を有する半導体デバイス、ディスプレイドライバ回路、及びディスプレイ装置
CN102569356A (zh) * 2010-12-29 2012-07-11 三星电子株式会社 具有保护环的半导体装置、显示驱动器电路和显示设备
TWI427783B (zh) * 2011-10-28 2014-02-21 Ti Shiue Biotech Inc 應用於分子檢測與鑑別的多接面結構之光二極體及其製造方法
US9860642B2 (en) * 2013-12-06 2018-01-02 Sharp Kabushiki Kaisha Audio wireless transmission system, speaker device, and source device
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CN108807155B (zh) * 2017-04-28 2020-10-30 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
JP7020280B2 (ja) * 2018-05-01 2022-02-16 日本精工株式会社 ラッチアップ防止回路
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CN114373746A (zh) * 2021-12-29 2022-04-19 无锡沐创集成电路设计有限公司 一种多熵源硬件真随机数发生器的熵源电路版图结构

Also Published As

Publication number Publication date
KR0139701B1 (ko) 1998-06-01
US5796147A (en) 1998-08-18
JP3210147B2 (ja) 2001-09-17
JPH0758289A (ja) 1995-03-03

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