KR940009078B1 - 반도체 기억 장치 - Google Patents
반도체 기억 장치 Download PDFInfo
- Publication number
- KR940009078B1 KR940009078B1 KR1019830003932A KR830003932A KR940009078B1 KR 940009078 B1 KR940009078 B1 KR 940009078B1 KR 1019830003932 A KR1019830003932 A KR 1019830003932A KR 830003932 A KR830003932 A KR 830003932A KR 940009078 B1 KR940009078 B1 KR 940009078B1
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- data line
- circuit
- timing
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000001514 detection method Methods 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000004044 response Effects 0.000 claims description 5
- 230000000295 complement effect Effects 0.000 description 88
- 230000003071 parasitic effect Effects 0.000 description 23
- 239000000872 buffer Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 7
- 230000003321 amplification Effects 0.000 description 5
- 239000006185 dispersion Substances 0.000 description 5
- 238000003708 edge detection Methods 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 230000008929 regeneration Effects 0.000 description 4
- 238000011069 regeneration method Methods 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 208000001034 Frostbite Diseases 0.000 description 1
- 229910021536 Zeolite Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- HNPSIPDUKPIQMN-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Al]O[Al]=O HNPSIPDUKPIQMN-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000010457 zeolite Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
Claims (2)
- 여러개의 다이나믹 메모리셀, 제1어드레스신호를 받고, 워드선(W1, W2, W3, W4)를 선택하는 것에 의해 상기 여러개의 다이나믹 메모리셀에서 상기 제1어드레스신호에 의해서 특정되는 것을 선택하고, 그 선택타이밍이 제1타이밍신호(φX)에 의해서 제어되는 제1선택회로(R-DCR), 상기 각 워드선(W1, W2, W3, W4)에 대응해서 마련되고, 리세트신호(φpw)에 동기해서 상기 워드선을 리세트상태로 하기 위한 MOSFET(Q1, Q2, Q3, Q4), 상기 다이나믹 메모리셀에 결합되는 것에 의해 선택된 다이나믹 메모리셀에서 리드된 데이타에 따른 전위차가 각각 공급되는 여러개의 데이타선쌍(D,), 각각이 대응하는 데이타선쌍(D,)에 결합되는 1쌍의 입출력단자를 갖고, 제2타이밍신호(φpa1, φpa2,)에 의해서 그들의 동작이 제어되는 여러 개의 센스앰프(SA), 상기 여러개의 데이타선쌍에 결합되고, 제3타이밍신호(φpc1)에 응답해서 상기 다이나믹 메모리셀에 축적된 2진신호의 중간전위로 프리차지하도록 동작하는 제1프리차지회로(PC1), 상기 제1어드레스신호를 구성하는 각 내부어드레스신호(a0∼ai)와 상기 각 내부어드레스신호의 지연신호와를 각각 받는 다수의 배타적 논리합회로(EX0∼EXi), 상기 다수의 배타적 논리합회로의 출력신호를 입력해서 검출신호를 출력하는 논리합회로(OR)를 포함하며, 상기 제1어드레스신호의 레벨변화를 검출하는 제1검출회로(EGTX), 상기 제1검출회로의 검출출력(φEX)를 받도록 결합되고, 상기 리세트신호(φpw), 상기 제1프리차지회로의 동작을 위한 상기 제3타이밍신호(φpc1), 상기 제1프리차지회로의 동작 정지후 상기 제1선택회로(R-DCR)의 동작을 위한 상기 제1타이밍신호(φX), 상기 센스앰프의 동작을 위한 상기 제2타이밍신호(φpa1, φpa2,를 발생하기 위한 수단(TG)를 포함하며, 상기 검출출력(φEX)에 따라서 상기 리세트신호(φpw)가 발생되고, 상기 워드선의 리세트가 종료하는 타이밍에 따라서 상기 제3타이밍신호(φpc1)이 발생되는 반도체기억장치.
- 특허청구의 범위 제1항에 있어서, 상기 각각의 다이나믹 메모리셀은 그의 게이트가 선택단자로써 사용되는 MOSFET와 상기 MOSFET에 결합된 전하유지용 커패시터로 구성되는 반도체기억장치.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920021527A KR970011023B1 (ko) | 1982-09-24 | 1992-11-17 | 반도체 기억장치 |
KR1019920021530A KR970011024B1 (ko) | 1982-09-24 | 1992-11-17 | 반도체 기억장치 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP164831 | 1982-09-24 | ||
JP57-164831 | 1982-09-24 | ||
JP57164831A JPS5956292A (ja) | 1982-09-24 | 1982-09-24 | 半導体記憶装置 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920021527A Division KR970011023B1 (ko) | 1982-09-24 | 1992-11-17 | 반도체 기억장치 |
KR1019920021530A Division KR970011024B1 (ko) | 1982-09-24 | 1992-11-17 | 반도체 기억장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR840005888A KR840005888A (ko) | 1984-11-19 |
KR940009078B1 true KR940009078B1 (ko) | 1994-09-29 |
Family
ID=15800754
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019830003932A Expired - Lifetime KR940009078B1 (ko) | 1982-09-24 | 1983-08-23 | 반도체 기억 장치 |
Country Status (10)
Country | Link |
---|---|
US (1) | US4564925A (ko) |
JP (1) | JPS5956292A (ko) |
KR (1) | KR940009078B1 (ko) |
DE (1) | DE3334560A1 (ko) |
FR (1) | FR2533739B1 (ko) |
GB (1) | GB2127640B (ko) |
HK (1) | HK70987A (ko) |
IT (1) | IT1167388B (ko) |
MY (1) | MY8700611A (ko) |
SG (1) | SG36787G (ko) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60136084A (ja) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | 半導体集積回路装置 |
JPS60211692A (ja) * | 1984-04-06 | 1985-10-24 | Hitachi Ltd | 半導体記憶装置 |
JPS60242587A (ja) * | 1984-05-16 | 1985-12-02 | Hitachi Micro Comput Eng Ltd | ダイナミツク型ram |
US4633102A (en) * | 1984-07-09 | 1986-12-30 | Texas Instruments Incorporated | High speed address transition detector circuit for dynamic read/write memory |
JPS6151692A (ja) * | 1984-08-22 | 1986-03-14 | Hitachi Ltd | 記憶装置 |
US4661931A (en) * | 1985-08-05 | 1987-04-28 | Motorola, Inc. | Asynchronous row and column control |
JPH0640439B2 (ja) * | 1986-02-17 | 1994-05-25 | 日本電気株式会社 | 半導体記憶装置 |
JPH06101229B2 (ja) * | 1986-09-09 | 1994-12-12 | 三菱電機株式会社 | ダイナミツク・ランダム・アクセス・メモリ |
US4780850A (en) * | 1986-10-31 | 1988-10-25 | Mitsubishi Denki Kabushiki Kaisha | CMOS dynamic random access memory |
JPS63138598A (ja) * | 1986-11-28 | 1988-06-10 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
JPH01251496A (ja) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | スタティック型ランダムアクセスメモリ |
JP2892757B2 (ja) * | 1990-03-23 | 1999-05-17 | 三菱電機株式会社 | 半導体集積回路装置 |
DE4228213C2 (de) * | 1991-09-19 | 1997-05-15 | Siemens Ag | Integrierte Halbleiterspeicherschaltung und Verfahren zu ihrem Betreiben |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5240937B2 (ko) * | 1972-05-16 | 1977-10-15 | ||
US3806898A (en) * | 1973-06-29 | 1974-04-23 | Ibm | Regeneration of dynamic monolithic memories |
US4156938A (en) * | 1975-12-29 | 1979-05-29 | Mostek Corporation | MOSFET Memory chip with single decoder and bi-level interconnect lines |
JPS5914827B2 (ja) * | 1976-08-23 | 1984-04-06 | 株式会社日立製作所 | アドレス選択システム |
DE2935121A1 (de) * | 1978-09-07 | 1980-03-27 | Texas Instruments Inc | Schreib/lese-halbleiterspeicher |
US4339809A (en) * | 1980-09-19 | 1982-07-13 | Rca Corporation | Noise protection circuits |
US4338679A (en) * | 1980-12-24 | 1982-07-06 | Mostek Corporation | Row driver circuit for semiconductor memory |
DE3101520A1 (de) * | 1981-01-19 | 1982-08-26 | Siemens AG, 1000 Berlin und 8000 München | Monolithisch integrierter halbleiterspeicher |
JPS57186289A (en) * | 1981-05-13 | 1982-11-16 | Hitachi Ltd | Semiconductor memory |
-
1982
- 1982-09-24 JP JP57164831A patent/JPS5956292A/ja active Pending
-
1983
- 1983-08-04 FR FR838312884A patent/FR2533739B1/fr not_active Expired - Lifetime
- 1983-08-23 KR KR1019830003932A patent/KR940009078B1/ko not_active Expired - Lifetime
- 1983-09-21 GB GB08325232A patent/GB2127640B/en not_active Expired
- 1983-09-23 US US06/535,056 patent/US4564925A/en not_active Expired - Fee Related
- 1983-09-23 DE DE19833334560 patent/DE3334560A1/de not_active Withdrawn
- 1983-09-23 IT IT22980/83A patent/IT1167388B/it active
-
1987
- 1987-04-23 SG SG367/87A patent/SG36787G/en unknown
- 1987-10-01 HK HK709/87A patent/HK70987A/xx unknown
- 1987-12-30 MY MY611/87A patent/MY8700611A/xx unknown
Also Published As
Publication number | Publication date |
---|---|
DE3334560A1 (de) | 1984-04-05 |
MY8700611A (en) | 1987-12-31 |
FR2533739B1 (fr) | 1991-06-07 |
IT8322980A0 (it) | 1983-09-23 |
GB2127640A (en) | 1984-04-11 |
JPS5956292A (ja) | 1984-03-31 |
IT1167388B (it) | 1987-05-13 |
US4564925A (en) | 1986-01-14 |
GB2127640B (en) | 1986-01-02 |
KR840005888A (ko) | 1984-11-19 |
HK70987A (en) | 1987-10-09 |
FR2533739A1 (fr) | 1984-03-30 |
GB8325232D0 (en) | 1983-10-26 |
SG36787G (en) | 1987-07-24 |
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Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19830823 |
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