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KR930020736A - CMOS fabrication method to increase junction breakdown voltage - Google Patents

CMOS fabrication method to increase junction breakdown voltage Download PDF

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Publication number
KR930020736A
KR930020736A KR1019920005393A KR920005393A KR930020736A KR 930020736 A KR930020736 A KR 930020736A KR 1019920005393 A KR1019920005393 A KR 1019920005393A KR 920005393 A KR920005393 A KR 920005393A KR 930020736 A KR930020736 A KR 930020736A
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KR
South Korea
Prior art keywords
well
active region
photoresist
injecting
forming
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KR1019920005393A
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Korean (ko)
Inventor
엄재철
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김주용
현대전자산업 주식회사
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Priority to KR1019920005393A priority Critical patent/KR930020736A/en
Priority to JP5073879A priority patent/JPH0613562A/en
Publication of KR930020736A publication Critical patent/KR930020736A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 접합 항복 전압을 증가시키는 CMOS제작방법에 관한 것으로,n+활성영역과 p+활성영역과 n+필드 스톱 임플랜트 영역, 그리고 p+활성영역과 n+필등 스톱 임플랜트 영영기 직접 만나지 않도록 n- 스페이서 내에는 n+활성영역을, p-스페이서 내에는 p+활성영역을 각각 마스크 패턴함으로서 접합항복 전압을 높이는 것으로 반도체 기판(1)에 p-웰(2)과, n-웰(3)을 형성하는 제1공정, 상기 제1공정후에 각소자의 격리특성을 향상시키기 위해 n+및 p+필드스톱 임플랜트(4,5)를주입하여 격리시키는 제2공정, 상기 제2공정후에 NMOS 및 PMOS의 게이트 산화막(7) 및 게이트(6)를 형성하는 제3공정, 상기 제3공정후에 상기 n-웰상(3)포토레지스트를 입히고 p-웰(2)에 n-불순물을 주입하는 제4공정, 상기 제4공정후에 상기 p-웰(2)상에 포토레지스틀 입히고 상기 n-웰(3)에 p-불순물을 주입하는 제5공정, 상기 제5공정후에 상기 n-웰(3)에 포토레지스트를 입히고 상기 p-웰(2)의 n-활성영역(16) 안쪽으로 n+불순물을 주입하는 제6공정, 상기 제6공정후에 상기 p-웰(2)상에 포토레지스트를 입히고 상기 n-웰(3)의 p-활성영역(17) 안쪽으로 p+불순물을 주입하는 제7공정, 상기 제7공정후에 산화물(18)을 도포하는 제8공정, 상기 제8공정후에 상기 n+및 p+활성영역(9,10)에 금속 접촉을 하도록 마스크 패턴하여 상기 산화물(18)을 식각하는 제9공정, 및 상기 산화물(18)을 식각한 후에 금속(11)을 접촉시키는 제10공정에 의해 이루어지는 것을 특징으로 한다.The present invention relates to a CMOS fabrication method for increasing a junction breakdown voltage, wherein n + active region, p + active region, n + field stop implant region, and p + active region and n + peel stop implant receivers do not meet directly. By increasing the junction breakdown voltage by mask patterning n + active region in the spacer and p + active region in the p-spacer, the p-well 2 and the n-well 3 in the semiconductor substrate 1 are increased. A first step of forming a second step of implanting and isolating n + and p + field stop implants 4 and 5 to improve the isolation characteristics of each device after the first step, and NMOS and A third step of forming the gate oxide film 7 and the gate 6 of the PMOS, and a fourth step of coating the n-well phase 3 photoresist and injecting n-impurities into the p-well 2 after the third step. After the fourth step, a photoresist is applied on the p-well 2 and the n-well 3 a fifth step of injecting p-impurity, a second step of applying photoresist to the n-well 3 after the fifth step and injecting n + impurity into the n-active region 16 of the p-well 2 A seventh step of applying a photoresist onto the p-well 2 after the sixth step and injecting p + impurities into the p-active region 17 of the n-well 3; An eighth step of applying the oxide 18 after the seventh step, and a ninth step of etching the oxide 18 by masking the metal contact to the n + and p + active regions 9 and 10 after the eighth step. And a tenth step of bringing the metal 11 into contact after the oxide 18 is etched.

Description

접합 항복 전압(junction breakdown voltage)을 높이는 CMOS 제조방법CMOS fabrication method to increase junction breakdown voltage

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 트랜지스터 제작공정도이다.3 is a transistor manufacturing process diagram of the present invention.

제4도는 계단형 접합에 있어서 불순물 농도 대비 어밸런치(avalanche)항복 전압 그래프이다.4 is a graph of avalanche breakdown voltage versus impurity concentration in a stepped junction.

Claims (5)

접합 항복 전압을 높이는 CMOS 제조방법에 있어서, 반도체 기판(1)에 p-웰(2)과 n-웰(3)을 형성하는 제1공정, 상기 제1공정후에 각소자의 격리특성을 향상시키기 위해 n+및 p+필드스톱 임플랜트(4,5)를주입하여 격리시키는 제2공정, 상기 제2공정후에 NMOS 및 PMOS의 게이트 산화막(7) 및 게이트(6)를 형성하는 제3공정, 상기 제3공정후에 상기 n-웰(3)포토레지스트(18)를 형성하는 제3공정, 상기 제3공정 후에 상기 n-웰상(3)에 포토레지스트를 입히고 p-웰(2)에 n-불순물을 주입하는 제4공정, 상기 제4공정후에 상기 p-웰(2)상에 포토레지스틀 입히고 상기 n-웰(3)에 p-불순물을 주입하는 제5공정, 상기 제5공정후에 상기 n-웰(3)에 포토레지스트를 입히고 상기 p-웰(2)의 n-활성영역(16) 안쪽으로 n+불순물을 주입하는 제6공정, 상기 제6공정후에 상기 p-웰(2)상에 포토레지스트를 입히고 상기 n-웰(3)의 p-활성영역(17) 안쪽으로 p+불순물을 주입하는 제7공정, 상기 제7공정후에 산화물(18)을 도포하는 제8공정, 상기 제8공정후에 상기 n+및 p+활성영역(9,10)에 금속 접촉을 하도록 마스크 패턴하여 상기 산화물(18)을 식각하는 제9공정, 및 상기 산화물(18)을 식각한 후에 금속(11)을 접촉시키는 소오스 및 드레인을 형성하는 제10공정에 의해 이루어지는 것을 특징으로 하는 CMOS 제조방법.In the CMOS manufacturing method of increasing the junction breakdown voltage, the first step of forming the p-well 2 and the n-well 3 in the semiconductor substrate 1, and to improve the isolation characteristics of each device after the first step A second step of implanting and isolating the n + and p + fieldstop implants 4 and 5, and forming a gate oxide film 7 and a gate 6 of the NMOS and PMOS after the second step; A third step of forming the n-well 3 photoresist 18 after the third step; after the third step, a photoresist is applied on the n-well phase 3 and n-impurities in the p-well 2 A fourth step of injecting a photoresist into the p-well 2 after the fourth step, and a fifth step of injecting a p-impurity into the n-well 3 and n after the fifth step Applying a photoresist to the well (3) and injecting n + impurities into the n-active region (16) of the p-well (2), after the sixth step on the p-well (2) Photoresist After smashing the eighth step, the eighth step of applying the seventh step, the oxide (18) after said seventh step of implanting a p + dopant to the inside p- active region 17 of the n- well 3 a ninth process of etching the oxide 18 by mask patterning the n + and p + active regions 9 and 10 to metal contact, and a source of contacting the metal 11 after etching the oxide 18. And a tenth step of forming a drain. 제1항에 있어서, 제6공정 및 제7공정에서 형성되는 n+활성영역(9)과 p+활성영역(10)의 접합깊이가 n-활성영역(16)과 p-활성영역(17)의 깊이보다 각각 더 큰 것을 특징으로 하는 CMOS제조방법.The junction depth of n + active region 9 and p + active region 10 formed in the sixth and seventh processes is n-active region 16 and p-active region 17. CMOS manufacturing method, characterized in that each larger than the depth of. 제1항에 있어서, 상기 제4,5공정의 n-활성영역(16),p-활성영역(17)형성공정과 상기 제6,7의 n+활성영역(9), p+활성영역(10) 형성공정의 순서가 바뀌는 것을 특징으로 하는 CMOS 제조방법.The process of claim 1, wherein the process of forming the n − active region 16 and the p-active region 17 of the fourth and fifth processes and the n + active region 9 and p + active region 10) CMOS manufacturing method, characterized in that the order of forming process is changed. 제1항에 있어서, 상기 반도체 기판(1)은 n형 기판인 것을 특징으로 하는 CMOS 제조방법.A method according to claim 1, wherein the semiconductor substrate (1) is an n-type substrate. 제1항에 있어서, 상기 반도체 기판(1)은 p형 기판인 것을 특징으로 하는 CMOS제조방법.A method according to claim 1, wherein the semiconductor substrate (1) is a p-type substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920005393A 1992-03-31 1992-03-31 CMOS fabrication method to increase junction breakdown voltage KR930020736A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920005393A KR930020736A (en) 1992-03-31 1992-03-31 CMOS fabrication method to increase junction breakdown voltage
JP5073879A JPH0613562A (en) 1992-03-31 1993-03-31 Method for manufacturing CMOS transistor with increased junction breakdown voltage

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Application Number Priority Date Filing Date Title
KR1019920005393A KR930020736A (en) 1992-03-31 1992-03-31 CMOS fabrication method to increase junction breakdown voltage

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KR930020736A true KR930020736A (en) 1993-10-20

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KR0161885B1 (en) * 1995-12-26 1999-02-01 문정환 Semiconductor device and its manufacturing method
TWI584476B (en) * 2011-08-25 2017-05-21 聯華電子股份有限公司 High voltage metal-oxide-semiconductor transistor device and method of fabricating the same

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JPS5779667A (en) * 1980-11-05 1982-05-18 Fujitsu Ltd Manufacture of semiconductor device
JP2554361B2 (en) * 1988-07-13 1996-11-13 沖電気工業株式会社 Method for manufacturing semiconductor device
JPH0316123A (en) * 1989-03-29 1991-01-24 Mitsubishi Electric Corp Ion implantation method and semiconductor device manufactured using the method
JPH03120870A (en) * 1989-10-04 1991-05-23 Nec Corp Insulated-gate type semiconductor device

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