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KR960039345A - Input protection circuit and manufacturing method of semiconductor integrated circuit - Google Patents

Input protection circuit and manufacturing method of semiconductor integrated circuit Download PDF

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Publication number
KR960039345A
KR960039345A KR1019960013330A KR19960013330A KR960039345A KR 960039345 A KR960039345 A KR 960039345A KR 1019960013330 A KR1019960013330 A KR 1019960013330A KR 19960013330 A KR19960013330 A KR 19960013330A KR 960039345 A KR960039345 A KR 960039345A
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KR
South Korea
Prior art keywords
mos fet
protection circuit
input protection
electrically connected
drain
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KR1019960013330A
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Korean (ko)
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KR100212610B1 (en
Inventor
이사미 사까이
Original Assignee
가네꼬 히사시
닛본덴기 가부시끼가이샤
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Publication of KR960039345A publication Critical patent/KR960039345A/en
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Publication of KR100212610B1 publication Critical patent/KR100212610B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 입력 단자(11)에 전기적으로 접속된 소스, 및 접지선(14)에 전기적으로 접속된 드레인 및 게이트를 가진 제1 MOS FET(3), 입력단자(11)에 전기적으로 접속된 소스, 및 드레인 게이트를 가진 제2 MOS FET(2), 및 전원선(12)에 전기적으로 접속된 소스, 및 제2 MOS FET(2)의 드레인 및 게이트에 전기적으로 접속된 드레인 및 게이트를 가진 제3 MOS FET(1)을 포함하는 입력 보호 회로를 제공한다. 입력 보호 회로는 기생 p-MOS 트랜지스터를 내부 회로와 공유하므로, 더 이상 입력 보호 회로에서만 사용되는 기생 MOS 트랜지스터를 형성할 필요가 없다. 따라서, 입력 보호 회로는 종래의 입력 보호 회로에 비해 포토마스크 사용 단계 수를 줄일 수 있다. 게다가 기생 MOS 트랜지스터를 내부 회로와 공유하면, 소스전압 이상의 전압이 입력 단자에 인가되더라도 입력 단자로부터 전원선으로 전류가 흐르는 것을 방지할 수 있다. 따라서, 정전 파괴에 대한 내성을 증가시키고 신뢰도를 가진 저가의 집적 회로를 제조할 수 있다.The present invention includes a first MOS FET 3 having a source electrically connected to the input terminal 11 and a drain and a gate electrically connected to the ground line 14, a source electrically connected to the input terminal 11, And a third MOS FET 2 having a drain gate and a source electrically connected to the power source line 12 and a drain and gate electrically connected to the drain and gate of the second MOS FET 2, An input protection circuit including a MOS FET (1) is provided. Since the input protection circuit shares the parasitic p-MOS transistor with the internal circuit, it is no longer necessary to form a parasitic MOS transistor used only in the input protection circuit. Therefore, the input protection circuit can reduce the number of steps of using the photomask as compared with the conventional input protection circuit. Furthermore, sharing the parasitic MOS transistor with the internal circuit can prevent current from flowing from the input terminal to the power supply line even if a voltage higher than the source voltage is applied to the input terminal. Therefore, a low-cost integrated circuit with increased resistance to electrostatic breakdown and reliability can be manufactured.

Description

입력 보호 회로 및 반도체 집적 회로의 제조 방법Input protection circuit and manufacturing method of semiconductor integrated circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 따라 제조되는 입력 보호 회로의 회로도.Figure 3 is a circuit diagram of an input protection circuit fabricated in accordance with the present invention;

Claims (8)

입력 보호 회로에 있어서, 입력 단자(11)에 전기적으로 접속된 소스, 및 접지선(14)에 전기적으로 둘다 접속된 드레인 및 게이트를 가진 제1 MOS FET(3); 및 상기 입력 단자(11)에 전기적으로 접속된 소스, 및 드레인 및 게이트를 가진 제2 MOS FET(2); 및 전원선(12)에 전기적으로 접속된 소스, 및 상기 제2 MOS FET(2)의 드레인 및 게이트에 전기적으로 둘다 접속된 드레인 및 게이트를 가진 제3 MOS FET(1)을 포함하는 것을 특징으로 하는 입력 보호 회로.1. An input protection circuit comprising: a first MOS FET (3) having a source electrically connected to an input terminal (11) and a drain and a gate electrically connected to both of the ground lines (14); And a second MOS FET (2) having a source, a drain and a gate electrically connected to the input terminal (11); And a third MOS FET (1) having a source electrically connected to the power line (12) and a drain and a gate electrically connected to both the drain and the gate of the second MOS FET (2) Input protection circuit. 제1항에 있어서, 상기 제1 및 제2 MOS FET(3 및 2)는 저 임계값을 가지는 p-채널 기생 MOS FET인 것을 특징으로 하는 입력 보호 회로.2. The input protection circuit as claimed in claim 1, wherein the first and second MOS FETs (3 and 2) are p-channel parasitic MOS FETs having a low threshold value. 제1항에 또는 제2항에 있어서, 상기 제3 MOS FET(1)은 고 임계값을 가지는 n-채널 기생 MOS FET인 것을 특징으로 하는 입력 보호 회로.The input protection circuit according to claim 1 or 2, wherein the third MOS FET (1) is an n-channel parasitic MOS FET having a high threshold value. 내부 회로(30), 및 상기 내부 회로(30)를 보호하는 입력 보호 회로(25)를 포함하고, 입력들이 상기 입력 보호 회로(25)를 통해 상기 내부 회로(30)으로 전송되는 반도체 집적 회로에 있어서, 상기 내부 회로(30)은 상기 입력 보호 회로(25)와 공유되는 다수의 기생 MOS FET(1, 2 및 3)을 내부에 구비하고 있는 것을 특징으로 하는 반도체 집적 회로.A semiconductor integrated circuit comprising an internal circuit (30) and an input protection circuit (25) for protecting the internal circuit (30), wherein inputs are transmitted to the internal circuit (30) via the input protection circuit , Wherein the internal circuit (30) has therein a plurality of parasitic MOS FETs (1, 2, 3) shared by the input protection circuit (25). 제4항에 있어서, 상기 기생 MOS FET(1, 2 및 3)은 상기 내부 회로(30) 내에서 소자 분리용으로서 사용되는 트랜지스터인 것을 특징으로 하는 반도체 집적 회로.The semiconductor integrated circuit according to claim 4, wherein the parasitic MOS FETs (1, 2 and 3) are transistors used for device isolation in the internal circuit (30). 반도체 집적 회로를 제조하는 방법에 있어서, 반도체 기판(301)의 활성 영역 상에 질화막(303)을 선택적으로 형성하는 단계; 상기 질화막(303)이 상부에 형성된 영역 이외의 영역에 제1 불순물을 비교적 작은 도우즈량으로 주입하는 단계; 상기 질화막(303)을 마스크로서 사용하여 상기 반도체 기판(301)의 비활성 영역 상에 선택적으로 열 산화에 의해 필드 산화물(306)을 형성하는 단계; 제1 MOS FET(1)이 제조될 영역에서 선택적으로 상기 필드 산화물(306)과 상기 반도체 기판(301) 사이의 인터페이스에 제2 불순물의 제1 이온 주입을 수행하는 단계; 및 상기 제1 MOS FET(1) 및 제2 MOS FET(2)가 제조될 영역 이외의 제3 MOS FET(3)이 제조될 영역에서 선택적으로 상기 필드 산화물(306)과 상기 반도체 기판(301) 사이의 인터페이스에 제3 불순물의 제2 이온주입을 수행하는 단계를 포함하는 것을 특징으로 하는 반도체 집적 회로의 제조 방법.A method of manufacturing a semiconductor integrated circuit, comprising: selectively forming a nitride film (303) on an active region of a semiconductor substrate (301); Implanting a first impurity into a region other than a region where the nitride film 303 is formed on the nitride film 303 in a relatively small dose amount; Forming a field oxide (306) selectively on the inactive region of the semiconductor substrate (301) by thermal oxidation using the nitride film (303) as a mask; Selectively implanting a first ion implantation of a second impurity into an interface between the field oxide (306) and the semiconductor substrate (301) in a region where the first MOS FET (1) is to be fabricated; And the field oxide 306 and the semiconductor substrate 301 are selectively formed in a region where the third MOS FET 3 other than the region where the first MOS FET 1 and the second MOS FET 2 are to be fabricated, And performing a second ion implantation of the third impurity into the interface between the first impurity and the second impurity. 제6항에 있어서, 상기 반도체 기판(301)은 p형 실리콘 기판이며, 상기 제1 및 제3 불순물은 p형 불순물이며, 상기 제2 불순물은 n형 불순물인 것을 특징으로 하는 반도체 집적 회로의 제조 방법.The semiconductor integrated circuit according to claim 6, wherein the semiconductor substrate (301) is a p-type silicon substrate, the first and third impurities are p-type impurities, and the second impurity is n-type impurity Way. 제6항 또는 제7항에 있어서, 상기 제1 MOS FET(1)은 p채널 MOS FET이며, 상기 제2 MOS FET(2)는 n채널 MOS FET이며, 상기 제3 MOS FET(3)은 비교적 저 임계값을 가지는 n 채널 MOS FET인 것을 특징으로 하는 반도체 집적 회로 제조 방법.The semiconductor device according to claim 6 or 7, wherein the first MOS FET (1) is a p-channel MOS FET, the second MOS FET (2) is an n-channel MOS FET, Wherein the n-channel MOS FET is an n-channel MOS FET having a low threshold value. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960013330A 1995-04-28 1996-04-27 Input protection circuit and method of fabricating semiconductor integrated circuit KR100212610B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP95-106391 1995-04-28
JP7106391A JP2882309B2 (en) 1995-04-28 1995-04-28 Input protection circuit and method of manufacturing semiconductor integrated circuit device

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KR960039345A true KR960039345A (en) 1996-11-25
KR100212610B1 KR100212610B1 (en) 1999-08-02

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6288590B1 (en) * 1999-05-21 2001-09-11 Intel Corporation High voltage protection input buffer
ATE456861T1 (en) * 1999-06-01 2010-02-15 Imec ESD PROTECTION COMPONENT FOR MEDIUM TRIGGER VOLTAGE
US6181193B1 (en) * 1999-10-08 2001-01-30 International Business Machines Corporation Using thick-oxide CMOS devices to interface high voltage integrated circuits
JP3515725B2 (en) 2000-01-26 2004-04-05 Ｎｅｃ化合物デバイス株式会社 Low current amplifier circuit
US6842318B2 (en) 2001-03-15 2005-01-11 Microsemi Corporation Low leakage input protection device and scheme for electrostatic discharge
KR100791076B1 (en) * 2006-12-04 2008-01-03 삼성전자주식회사 Logic circuit having electric field reducing transistor and semiconductor device having same

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US4609931A (en) * 1981-07-17 1986-09-02 Tokyo Shibaura Denki Kabushiki Kaisha Input protection MOS semiconductor device with zener breakdown mechanism
EP0328905B1 (en) * 1988-02-15 1994-06-29 Siemens Aktiengesellschaft Circuit arrangement for the protection of an integrated circuit
US5272586A (en) * 1991-01-29 1993-12-21 National Semiconductor Corporation Technique for improving ESD immunity
JPH0563540A (en) * 1991-08-29 1993-03-12 Nec Corp Input circuit
US5532178A (en) * 1995-04-27 1996-07-02 Taiwan Semiconductor Manufacturing Company Gate process for NMOS ESD protection circuits

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US5696397A (en) 1997-12-09
JP2882309B2 (en) 1999-04-12
JPH08306799A (en) 1996-11-22
KR100212610B1 (en) 1999-08-02

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