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KR970003703A - Well forming method of MOS transistor - Google Patents

Well forming method of MOS transistor Download PDF

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Publication number
KR970003703A
KR970003703A KR1019950019148A KR19950019148A KR970003703A KR 970003703 A KR970003703 A KR 970003703A KR 1019950019148 A KR1019950019148 A KR 1019950019148A KR 19950019148 A KR19950019148 A KR 19950019148A KR 970003703 A KR970003703 A KR 970003703A
Authority
KR
South Korea
Prior art keywords
well
forming
wells
photoresist pattern
drive
Prior art date
Application number
KR1019950019148A
Other languages
Korean (ko)
Inventor
문환성
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950019148A priority Critical patent/KR970003703A/en
Publication of KR970003703A publication Critical patent/KR970003703A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0156—Manufacturing their doped wells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks

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  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

1. 청구 범위에 지재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 소자의 제조 방법.Method of manufacturing a semiconductor device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래의 MOSFET 소자의 웰 형성 방법은, P-웰과 N-웰의 단차가 심하여 고집적화에 어렵고, 특히 N-웰의 불순물을 확산 시키는 드라이브 인 공정이 약 20시간 이상이 소요되어 장시간의 반도체 소자의 제조 공정이 요구되는 문제점을 해결하고자 함.Conventional MOSFET device well formation method is difficult to high integration due to the severe step between P-well and N-well, and particularly, the drive-in process for diffusing impurities of N-well takes about 20 hours or more. To solve the problem that the manufacturing process is required.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

모스 트랜지스터의 N-웰 형성 수행시 암모니아 분위기의 드라이브 인 공정을 실시하여 모스 트랜지스터의 N-웰과 P-웰을 구분할 수 있을 정도로만 N-웰을 형성하여 웰간의 단차를 줄일 수 있는 모스 트랜지스터의 웰 형성 방법을 제공하고자 함.When performing N-well formation of MOS transistors, the wells of MOS transistors can be formed so that the N-wells can be formed only to distinguish the N-wells and P-wells of the MOS transistors by performing a drive-in process in an ammonia atmosphere. To provide a formation method.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 소자의 제조, 특히 모스 트랜지스터의 웰 형성에 이용됨.Used in the manufacture of semiconductor devices, in particular in the formation of wells of MOS transistors.

Description

모스 트랜지스터의 웰 형성방법Well forming method of MOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 모스 트랜지스터의 웰 형성 방법에 따른 공정도.2A to 2D are process diagrams according to the well forming method of the MOS transistor of the present invention.

Claims (1)

모스 트랜지스터의 웰 형성 방법에 있어서, 반도체 기판 상에 확산 장벽용 산화막, 질화막을 차례로 형성하는 단계와, N-웰 형성을 위한 제1포토레지스트 패턴을 형성하는 단계와, 상기 제1포토레지스트 패턴을 식각 배리어로 이용하여 상기 질화막을 식각하는 단계와, N-웰 형성을 위한 N형의 불순물 이온 주입을 실시하는 단계와, 상기 불순물 이온을 확산시켜 N-웰을 형성하기 위하여 약 1150℃의 온도에서 암모니아 분위기로 드라이브 인 공정을 실시하는 단계와, 상기 제1포토레지스트 패턴, 상기 질화막을 차례로 제거하고, P-웰 형성을 위한 제2포토레지스트 패턴을 형성한 후 P형의 불순물 이온 주입을 실시하는 단계와, 드라이브 인 공정을 수행하여 P-웰을 형성하는 단계와, 상기 제2포토레지스트 패턴, 상기 확산 장벽용 산화막과 N-웰 및 P-웰의 형성을 위한 드라이브 인 공정 수행시 형성되는 산화물 및 질화물을 제거하는 단계를 포함해서 이루어진 모스 트랜지스터의 웰 형성 방법.A method of forming a well of a MOS transistor, comprising: sequentially forming an oxide film for diffusion barrier and a nitride film on a semiconductor substrate, forming a first photoresist pattern for forming an N-well, and forming the first photoresist pattern. Etching the nitride film using an etch barrier, implanting an N-type impurity ion to form an N-well, and diffusing the impurity ions at a temperature of about 1150 ° C. to form an N-well. Performing a drive-in process in an ammonia atmosphere, sequentially removing the first photoresist pattern and the nitride film, forming a second photoresist pattern for forming a P-well, and then performing a P-type impurity ion implantation. And forming a P-well by performing a drive-in process, forming the second photoresist pattern, the oxide layer for diffusion barrier, the N-well, and the P-well. Removing the oxides and nitrides formed during the drive-in process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019148A 1995-06-30 1995-06-30 Well forming method of MOS transistor KR970003703A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019148A KR970003703A (en) 1995-06-30 1995-06-30 Well forming method of MOS transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019148A KR970003703A (en) 1995-06-30 1995-06-30 Well forming method of MOS transistor

Publications (1)

Publication Number Publication Date
KR970003703A true KR970003703A (en) 1997-01-28

Family

ID=66526040

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950019148A KR970003703A (en) 1995-06-30 1995-06-30 Well forming method of MOS transistor

Country Status (1)

Country Link
KR (1) KR970003703A (en)

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19950630

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid