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KR910001718B1 - Semiconductor integrated circuit devcie - Google Patents

Semiconductor integrated circuit devcie Download PDF

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Publication number
KR910001718B1
KR910001718B1 KR1019870009387A KR870009387A KR910001718B1 KR 910001718 B1 KR910001718 B1 KR 910001718B1 KR 1019870009387 A KR1019870009387 A KR 1019870009387A KR 870009387 A KR870009387 A KR 870009387A KR 910001718 B1 KR910001718 B1 KR 910001718B1
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South Korea
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sbd
collector
transistor
integrated circuit
semiconductor integrated
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KR880008453A (en
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쓰네히로 고야마
이찌로오 다끼요우
요시히꼬 히라다
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미쓰비시 뎅끼 가부시끼이샤
시기모리야
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/221Schottky barrier BJTs

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  • Electrodes Of Semiconductors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

반도체 집적 회로장치Semiconductor integrated circuit device

제1도(a)는 본 발명의 일실시예에 의한 SBD 트랜지스터를 표시한 평면도. (b)는 (a)도의 가-나선 단면도.1A is a plan view showing an SBD transistor according to an embodiment of the present invention. (b) is a helical cross-sectional view of (a).

제2도(a)는 종래의 SBD 트랜지스터를 표시한 상면도. (b)는 (a)도의 다-라선 단면도.Figure 2 (a) is a top view showing a conventional SBD transistor. (b) is a cross-sectional view taken along line (a) of FIG.

제3도는 종래 및 본 실시예의 SBD 트랜지스터를 표시한 회로도이다.3 is a circuit diagram showing the SBD transistors of the prior art and this embodiment.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 콜렉터부 N형 반도체층 2 : 베이스부 P형 반도체층DESCRIPTION OF SYMBOLS 1 Collector part N type semiconductor layer 2 Base part P type semiconductor layer

3 : 에미터부 N형 반도체층 4 : SBD부3: emitter portion N-type semiconductor layer 4: SBD portion

5 : 매입 콜렉터용 N형 반도체층 6 : N형 반도체 에픽택셜층5: N-type semiconductor layer for embedded collector 6: N-type semiconductor epitaxial layer

7 : 콘택트홀 8 : 산화막7: contact hole 8: oxide film

9 : 배선용금속 10 : 코너부9: wiring metal 10: corner

11 : SBD 12 : NPN 트랜지스터11: SBD 12: NPN transistor

본 발명은 쇼트키 배리어 다이오드(Schottky Barrier Diode)클램프트 트랜지스터에 관한 것으로 특히 그 출력 리이크(Leak)전류를 감소시킨것에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to Schottky Barrier Diode clamp transistors, and more particularly to reducing the output leakage current thereof.

종래의 쇼트키 배리어 다이오드를램프츠 트렌지스터로써 예를 들면 '85미쓰비시 반도체 베이터북 바이폴러 디지탈 1C<LSTTL>편(1∼12페이지)에 표시된 구조의 것을 예로하여 제2도를 참조하여 설명한다. 제2도(a)는 평면도, 제2도(b)는 측면도이다. 또 제3도는 그 등가회로도이다.A conventional Schottky barrier diode will be described with reference to FIG. 2 by taking an example of the structure shown in, for example, a '85 Mitsubishi Semiconductor Batterbook Bipolar Digital 1C <LSTTL> section (pages 1 to 12) as a lamps transistor. FIG. 2A is a plan view and FIG. 2B is a side view. 3 is an equivalent circuit diagram.

도면에 있어서 1은 콜렉터부 형반도체층, 2는 베이스부 P형 반도체층, 3은 에미터부 N형 반도체층, 4는 쇼트키 배리어 다이오드(이하 SBD라고 칭한다)부 5는 매입 콜렉터층, 6은 N형반도체 에픽택셜층, 7은 SDB부(4) 및 베이스 콘택트를 형성하기위한 콘택트홀 10은 콘택트홀(7)의 코너부, 11은 SBD, 12는 NPN트랜지스터; 9는 배선용 금속으로, 베이스부에서는 NPN 트랜지스터 (12)의 베이스와 SBD(11)의 애노드가 쇼트되어 있다. 8은 배선용금속(9)과 반도체 표면간을 절연하기 인한 산화막이다.In the drawings, 1 is a collector portion semiconductor layer, 2 is a base portion P-type semiconductor layer, 3 is an emitter portion N-type semiconductor layer, 4 is a Schottky barrier diode (hereinafter referred to as SBD) portion 5 is an embedded collector layer, 6 is An N-type semiconductor epitaxial layer, 7 is an SDB portion 4 and a contact hole 10 for forming a base contact is a corner portion of the contact hole 7, 11 is an SBD, 12 is an NPN transistor; 9 is a wiring metal, and the base part of the NPN transistor 12 and the anode of the SBD 11 are short-circuited. 8 is an oxide film which insulates between the wiring metal 9 and the semiconductor surface.

다음은 동작에 대하여 설명한다.The following describes the operation.

SBD 트랜지스터는 NPN 트랜지스턴(12)가 온할때 콜렉터의 전위가 SBD(11)에서 클램프되기 때문에 트랜지스터의 축적시간을 단축할 수 있다.The SBD transistor can shorten the accumulation time of the transistor because the potential of the collector is clamped in the SBD 11 when the NPN transistor 12 is turned on.

그러나 SBD(11)의 역방향 특성에 리이크가 있을경우 콜렉처의 리이프전류(I)는However, if there is a leak in the reverse characteristic of the SBD 11, the relief current I of the collector is

I=Ileak+ICIleak,Ileak+hfe· Ileak I = I leak + ICI leak, I leak + h fe · I leak

=Ileak(1 +hFE)= I leak (1 + h FE )

가 되고 hFE=100이라면 I=100xIleak가 되고 Ileak가 미소하더라도 콜렉터의 리이크전류는 무시할 수 없는 것이된다.If h FE = 100, then I = 100xI leak , and even if the I leak is minute, the collector current cannot be ignored.

일반적으로 SBD의 리인크전류는 제조방법에 기인하는 것으로 콜랙트홀(7)의 외주부에서 리이크전류가 대부분이고 특히 콘택트홀(7)의 코너부(10)에서의 리이크전류가 압도적으로 많다.In general, the leakage current of the SBD is due to the manufacturing method, and the leakage current is mostly at the outer circumferential portion of the collector hole 7, and the leakage current at the corner portion 10 of the contact hole 7 is predominantly large.

종래의 SBD 트랜지스터는 이상과 같이 구성되어 있으므로, 콘택트홀의 외주부, 특히 코너부분에서의 리이크전류가 SBD 전체의 리이코전류중에서 지배적이고 PN다이오드와 비교하여 리이크전류는 1자리이상 커서 SBD 트랜지스터의 콜렉터 리이코전류가 크게되는 문제점이 있다.Since the conventional SBD transistor is constructed as described above, the leakage current at the outer peripheral part of the contact hole, especially the corner part, is dominant among the Ricoh currents of the entire SBD, and the leakage current is one or more digits in comparison with the PN diode. There is a problem that the collector Rico current is large.

본 발명은 상기와 같은 문제점을 해소하기 위하여 창안된 것으로서 패턴사이즈를 넓히는 일없이 콜렉터의 리이크전류를 작게할 수 있는 SBI) 트랜지스터를 얻는것을 목적으로 한것이다.The present invention has been made to solve the above problems, and an object thereof is to obtain an SBI) transistor capable of reducing the collector current of a collector without increasing the pattern size.

본 발명에 관한 반도체 집적회로는 SBD를 형성하기 위한 콘택트홀의 코너부분의 형상을 원호형상으로 한것이다.In the semiconductor integrated circuit according to the present invention, the shape of the corner portion of the contact hole for forming the SBD is arc-shaped.

본 발명에 있어서는 SBD를 형성하기위한 콘택트홀의 코너부분의 형상을 원호형상으로 하였으므로 리이크전류의 집중부분이 없게되어 콜렉터 리이크전류를 작게 할 수가 있다.In the present invention, since the shape of the corner portion of the contact hole for forming the SBD is arc-shaped, there is no concentrated portion of the leak current, so that the collector leak current can be reduced.

이하 본 발명의 일실시예를 도면에 따라 설명한다.Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

제1도(a) 및 (b)는 본 발명의 일실시예에 의한 SBD 트랜지스터의 평면도 및 단면도이고, 도면에 있어서 제2도와 동일부호는 동일의 것을 표시하고 7은 SBD부(4)를 형성하기위한 콘택트홀이며, 그 코너부(10)의 형상은 원호형상으로 되어있다.1 (a) and (b) are a plan view and a cross-sectional view of an SBD transistor according to an embodiment of the present invention, in which the same reference numerals as those in FIG. 2 denote the same, and 7 forms the SBD portion 4. It is a contact hole for the purpose, The shape of the corner part 10 is circular arc shape.

이와 같이 구성된 반도체 집적회로장치에서는 콘택트흘(7)의 코너부(10)의 형상을 원호형상으로 하므로서 리이크전류가 압도적으로 많이 흐르는 부분인 예각상태의 코너부가 없어지므로 리이크전류의 집중부분이 없 게되고 콜렉터 리이크전류를 제거할 수가 있다.In the semiconductor integrated circuit device configured as described above, the corner portion 10 of the contact flow 7 is arcuated, and the corner portion of the acute angle, which is a portion where the leakage current flows predominantly, is eliminated. It can eliminate the collector leakage current.

또한 콘택트홀(7)의 코너부(10)의 형상을 원호형상으로 한것뿐이므로 패턴사이즈를 대략 크게 할 필요는 없고 더우기 종래와 같은 용이하게 마스크워크를 할 수가 있다.In addition, since only the shape of the corner portion 10 of the contact hole 7 is in the shape of an arc, it is not necessary to increase the pattern size substantially, and moreover, maskwork can be easily performed as in the prior art.

이상과 같이 본 발명의 반도체 집적회로장치에 의하여 SBD를 형성하기위한 콘택트홀의 코너부분의 형상을 원호형상으로 하였으므로 트린지스터 사이즈를 증대하는일없이 콜렉터의 리이크전류를 작게할 수 있는 효과가 있다.As described above, since the shape of the corner portion of the contact hole for forming the SBD by the semiconductor integrated circuit device of the present invention is an arc shape, there is an effect that the leak current of the collector can be reduced without increasing the transistor size.

Claims (1)

NPN 트랜지스터의 베이스와 쇼트키 배리어 다이오드의 애노드가 접속되고 이 트랜지스터의 콜렉터와 이 쇼트키 배히어 다이오드의 캐소드가 접속된 쇼트키 배리어 다이오드 을램프트 트랜지스터에 있어서 상기 쇼트키 배리어 다이오드를 형성하기위한 콘택트홀은 원호형상의 코너부분을 보유하도록 된것을 특징으로 하는 반도체집적회로장치.A Schottky barrier diode in which the base of the NPN transistor is connected to the anode of the Schottky barrier diode, and the collector of the transistor and the cathode of the Schottky Baherier diode is connected to the contact for forming the Schottky barrier diode in the ramp transistor. And the hole is configured to hold an arc-shaped corner portion.
KR1019870009387A 1986-12-08 1987-08-27 Semiconductor integrated circuit devcie Expired KR910001718B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61292729A JPS63143867A (en) 1986-12-08 1986-12-08 Semiconductor integrated circuit device
JP61-292729 1986-12-08

Publications (2)

Publication Number Publication Date
KR880008453A KR880008453A (en) 1988-08-31
KR910001718B1 true KR910001718B1 (en) 1991-03-19

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KR1019870009387A Expired KR910001718B1 (en) 1986-12-08 1987-08-27 Semiconductor integrated circuit devcie

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KR (1) KR910001718B1 (en)
DE (1) DE3741567A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110752256A (en) * 2019-10-22 2020-02-04 深圳第三代半导体研究院 Silicon carbide Schottky clamp transistor and preparation method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54154967A (en) * 1978-05-29 1979-12-06 Nippon Telegr & Teleph Corp <Ntt> Semiconductor electronic device
JPS59139681A (en) * 1983-01-31 1984-08-10 Hitachi Ltd Schottky barrier diode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110752256A (en) * 2019-10-22 2020-02-04 深圳第三代半导体研究院 Silicon carbide Schottky clamp transistor and preparation method thereof
CN110752256B (en) * 2019-10-22 2021-04-06 深圳第三代半导体研究院 Silicon carbide Schottky clamp transistor and preparation method thereof

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Publication number Publication date
DE3741567A1 (en) 1988-06-09
JPS63143867A (en) 1988-06-16
DE3741567C2 (en) 1992-11-19
KR880008453A (en) 1988-08-31

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