KR20010039747A - 미소전자기판 상의 지형 효과 보정 방법 - Google Patents
미소전자기판 상의 지형 효과 보정 방법 Download PDFInfo
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- KR20010039747A KR20010039747A KR1020000042258A KR20000042258A KR20010039747A KR 20010039747 A KR20010039747 A KR 20010039747A KR 1020000042258 A KR1020000042258 A KR 1020000042258A KR 20000042258 A KR20000042258 A KR 20000042258A KR 20010039747 A KR20010039747 A KR 20010039747A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
- H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (7)
- 미소전자기판 상의 지형 효과를 보정하기 위한 방법에 있어서,i) 고립영역으로 에워싸이고 양각의 지형을 가지는 평탄화될 구조에 제1 층의 수지(200)를 침적시키는 단계와,ⅱ) 하부에 놓이는 고립영역 보다 작은 크기의 수지 패턴을 부과하는 마스크에 의해 마스크되는 사진석판술로 하부에 놓이는 저밀도 지형 영역에 걸쳐서 중첩되는 영역에 상기 수지 층(200)을 위치시키는 단계와,ⅲ) 하부에 놓이는 지형과 일대일 대응 없이 표준 메쉬를 처리하는 마스크를 통해 사진석판술로 하부에 놓이는 고밀도 지형 영역에 걸쳐서 중첩되는 영역에 상기 수지 층(200)을 위치시키는 단계와,ⅳ) 제1 수지 층의 생성 영역이 고립영역을 덮도록 열적 흐름으로 사진 석판될 때 상기 제1 수지 층(200)을 위치시키는 단계와,ⅴ) 제2의 수지 층(210)을 침적시키는 단계와,ⅵ) 플라즈마 에칭을 행하는 단계와, 그리고ⅶ) 기계적 화학적 연마를 행하는 단계로 구성되며, 표준 메쉬를 처리하는 마스크를 통한 사진 석판의 상기 단계 ⅲ)는 큰 지형의 조밀한 영역을 최적으로 채움으로써 얻기 위한 고립구조를 조정하는 단계로 구성되는 것을 특징으로 하는 미소전자기판 상의 지형 효과 보정 방법.
- 제1항에 있어서,단계 ⅱ) 및 단계 ⅲ)는 하부 지형의 저밀도영역과 고밀도영역에 제공된 공통 마스크를 이용하여 행해지는 것을 특징으로 하는 미소전자기판 상의 지형 효과 보정 방법.
- 제1항에 있어서,단계 ⅱ) 및 단계 ⅲ)는 별개의 마스크를 이용하여 행해지는 것을 특징으로 하는 미소전자기판 상의 지형 효과 보정 방법.
- 제1항 내지 제3항 중 어느 한 항에 있어서,상기 마스크 형성수단은 상기 수지 층(200)을 소형의 고립된 고립 영역 형태로부터 배제하기에 적합한 것을 특징으로 하는 미소전자기판 상의 지형 효과 보정 방법.
- 제1항 내지 제4항 중 어느 한 항에 있어서,단계 ⅲ)에서 사용된 상기 마스크 형성수단은 라인의 격자를 갖는 것을 특징으로 하는 미소전자기판 상의 지형 효과 보정 방법.
- 제1항 내지 제5항 중 어느 한 항에 있어서,단계 ⅲ)에서 사용된 상기 마스크 형성수단은 서로 대해 45。의 격자 라인을 갖는 것을 특징으로 하는 미소전자기판 상의 지형 효과 보정 방법.
- 제1항 내지 제6항 중 어느 한 항에 있어서,상기 마스크 형성수단은 2㎛ 로 이격되고 두께가 0.5 ㎛인 라인을 갖는 것을 특징으로 하는 미소전자기판 상의 지형 효과 보정 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9909521A FR2796758B1 (fr) | 1999-07-22 | 1999-07-22 | Procede de correction des effets topographiques sur substrat en micro electronique |
FR9909521 | 1999-07-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010039747A true KR20010039747A (ko) | 2001-05-15 |
KR100688122B1 KR100688122B1 (ko) | 2007-02-28 |
Family
ID=9548403
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000042258A Expired - Fee Related KR100688122B1 (ko) | 1999-07-22 | 2000-07-22 | 미소전자기판 상의 지형 효과 보정 방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6387808B1 (ko) |
EP (1) | EP1071122B1 (ko) |
JP (1) | JP4578635B2 (ko) |
KR (1) | KR100688122B1 (ko) |
FR (1) | FR2796758B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104465315A (zh) * | 2013-09-24 | 2015-03-25 | 工业和信息化部电子第五研究所 | 3d叠层芯片封装器件的芯片分离方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004304152A (ja) * | 2003-03-20 | 2004-10-28 | Seiko Epson Corp | 半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
US7262070B2 (en) * | 2003-09-29 | 2007-08-28 | Intel Corporation | Method to make a weight compensating/tuning layer on a substrate |
FR2910180A1 (fr) * | 2006-12-15 | 2008-06-20 | St Microelectronics | Procede de fabrication d'un transistor cmos a grilles metalliques duales. |
EP2209905A4 (en) * | 2007-10-17 | 2010-10-06 | 3M Innovative Properties Co | RAPID DETECTION OF MICROORGANISMS |
KR101860493B1 (ko) * | 2011-10-20 | 2018-05-24 | 삼성디스플레이 주식회사 | 미세 패턴 마스크의 형성 방법 및 이를 이용한 미세 패턴의 형성 방법 |
CN102768944A (zh) * | 2012-07-03 | 2012-11-07 | 上海华力微电子有限公司 | 一种修补去层次样品的方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0145369B1 (ko) * | 1993-11-17 | 1998-08-17 | 가네꼬 히사시 | 반도체 장치의 제조방법 |
JP2555958B2 (ja) * | 1993-11-17 | 1996-11-20 | 日本電気株式会社 | 半導体装置の製造方法 |
US5925494A (en) * | 1996-02-16 | 1999-07-20 | Massachusetts Institute Of Technology | Vapor deposition of polymer films for photolithography |
JPH09321043A (ja) * | 1996-05-28 | 1997-12-12 | Toshiba Corp | 半導体装置の製造方法 |
US6316363B1 (en) * | 1999-09-02 | 2001-11-13 | Micron Technology, Inc. | Deadhesion method and mechanism for wafer processing |
US6174449B1 (en) * | 1998-05-14 | 2001-01-16 | Micron Technology, Inc. | Magnetically patterned etch mask |
US6258514B1 (en) * | 1999-03-10 | 2001-07-10 | Lsi Logic Corporation | Top surface imaging technique using a topcoat delivery system |
US6207555B1 (en) * | 1999-03-17 | 2001-03-27 | Electron Vision Corporation | Electron beam process during dual damascene processing |
JP5580826B2 (ja) * | 2009-08-11 | 2014-08-27 | 浜松ホトニクス株式会社 | レーザ加工装置及びレーザ加工方法 |
-
1999
- 1999-07-22 FR FR9909521A patent/FR2796758B1/fr not_active Expired - Fee Related
-
2000
- 2000-07-19 JP JP2000219525A patent/JP4578635B2/ja not_active Expired - Fee Related
- 2000-07-19 EP EP00402053A patent/EP1071122B1/fr not_active Expired - Lifetime
- 2000-07-21 US US09/620,896 patent/US6387808B1/en not_active Expired - Fee Related
- 2000-07-22 KR KR1020000042258A patent/KR100688122B1/ko not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104465315A (zh) * | 2013-09-24 | 2015-03-25 | 工业和信息化部电子第五研究所 | 3d叠层芯片封装器件的芯片分离方法 |
Also Published As
Publication number | Publication date |
---|---|
US6387808B1 (en) | 2002-05-14 |
FR2796758A1 (fr) | 2001-01-26 |
FR2796758B1 (fr) | 2003-02-14 |
JP4578635B2 (ja) | 2010-11-10 |
EP1071122B1 (fr) | 2004-05-12 |
KR100688122B1 (ko) | 2007-02-28 |
JP2001077021A (ja) | 2001-03-23 |
EP1071122A1 (fr) | 2001-01-24 |
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