KR101910100B1 - Soi 웨이퍼의 제조방법 - Google Patents
Soi 웨이퍼의 제조방법 Download PDFInfo
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- KR101910100B1 KR101910100B1 KR1020157005866A KR20157005866A KR101910100B1 KR 101910100 B1 KR101910100 B1 KR 101910100B1 KR 1020157005866 A KR1020157005866 A KR 1020157005866A KR 20157005866 A KR20157005866 A KR 20157005866A KR 101910100 B1 KR101910100 B1 KR 101910100B1
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000005468 ion implantation Methods 0.000 claims abstract description 38
- 239000001257 hydrogen Substances 0.000 claims abstract description 20
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 20
- 239000013078 crystal Substances 0.000 claims abstract description 17
- 239000007789 gas Substances 0.000 claims abstract description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000001307 helium Substances 0.000 claims description 31
- 229910052734 helium Inorganic materials 0.000 claims description 31
- -1 hydrogen ions Chemical class 0.000 claims description 31
- 238000002513 implantation Methods 0.000 claims description 10
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 238000005530 etching Methods 0.000 description 12
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 9
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
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- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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Abstract
Description
도 2는 실시예 1 및 비교예 1에 있어서의 박리 후의 SOI층 막두께 분포의 측정결과를 나타낸 도면이다.
도 3은 비교예 2의 SOI 웨이퍼의 중앙부에 발생한 SOI 막두께 이상과 스크래치를 나타낸 도면이다.
도 4는 종래의 공주입을 이용한 SOI 웨이퍼의 제조방법의 일예를 나타낸 플로우도이다.
Claims (8)
- 반도체 단결정 기판으로 이루어진 본드 웨이퍼에 산화막을 형성하고, 이 산화막을 통해 수소 및 희가스 중 적어도 1종류의 가스이온을 이온주입하여 상기 본드 웨이퍼에 이온주입층을 형성하고, 이 본드 웨이퍼의 이온주입한 표면과 베이스 웨이퍼 표면을 상기 산화막을 개재하여 접합한 후, 상기 이온주입층에서 상기 본드 웨이퍼를 박리함으로써 SOI 웨이퍼를 제작하는 SOI 웨이퍼의 제조방법에 있어서,
접합 전에, 상기 본드 웨이퍼에 형성하는 산화막을, 접합면의 산화막보다 배면의 산화막을 두껍게 하고, 이 배면의 산화막을 두껍게 한 본드 웨이퍼에 이온주입한 후 베이스 웨이퍼와 접합하는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
- 제1항에 있어서,
상기 본드 웨이퍼의 산화막의 형성은, 본드 웨이퍼의 전체면에 열산화막을 형성한 후, 이 본드 웨이퍼의 접합면측의 열산화막을 제거함으로써 배면에만 열산화막을 갖는 본드 웨이퍼를 제작하고, 이 배면에만 열산화막을 갖는 본드 웨이퍼의 전체면을 열산화함으로써 행하는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
- 제2항에 있어서,
상기 본드 웨이퍼의 접합면측의 열산화막을 제거한 후에, 이 접합면측을 연마하는 공정을 포함하고, 그 후 전체면의 열산화를 행하는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
- 제1항 내지 제3항 중 어느 한 항에 있어서,
상기 본드 웨이퍼로서, 이온주입층에서 박리 후의 본드 웨이퍼를 재생가공하여 제작한 웨이퍼를 이용하는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
- 제4항에 있어서,
상기 재생가공에 있어서, 상기 박리 후의 본드 웨이퍼의 배면산화막을 제거하지 않은 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
- 제1항 내지 제3항 중 어느 한 항에 있어서,
상기 이온주입으로서, 수소이온과 헬륨이온의 공주입을 행하고, 이 공주입에 있어서 헬륨이온을 수소이온보다 깊은 위치에 주입하는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
- 제4항에 있어서,
상기 이온주입으로서, 수소이온과 헬륨이온의 공주입을 행하고, 이 공주입에 있어서 헬륨이온을 수소이온보다 깊은 위치에 주입하는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
- 제5항에 있어서,
상기 이온주입으로서, 수소이온과 헬륨이온의 공주입을 행하고, 이 공주입에 있어서 헬륨이온을 수소이온보다 깊은 위치에 주입하는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
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JPJP-P-2012-255719 | 2012-11-21 | ||
JP2012255719A JP5821828B2 (ja) | 2012-11-21 | 2012-11-21 | Soiウェーハの製造方法 |
PCT/JP2013/006072 WO2014080563A1 (ja) | 2012-11-21 | 2013-10-11 | Soiウェーハの製造方法 |
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KR20150087181A KR20150087181A (ko) | 2015-07-29 |
KR101910100B1 true KR101910100B1 (ko) | 2018-10-19 |
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US (1) | US9378999B2 (ko) |
EP (1) | EP2924736B1 (ko) |
JP (1) | JP5821828B2 (ko) |
KR (1) | KR101910100B1 (ko) |
CN (1) | CN104620384B (ko) |
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WO (1) | WO2014080563A1 (ko) |
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JP6353814B2 (ja) * | 2015-06-09 | 2018-07-04 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
JP6556511B2 (ja) * | 2015-06-17 | 2019-08-07 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN110085549B (zh) * | 2018-01-26 | 2021-06-04 | 沈阳硅基科技有限公司 | 一种双面注入得到soi的方法 |
CN110544668B (zh) * | 2018-05-28 | 2022-03-25 | 沈阳硅基科技有限公司 | 一种通过贴膜改变soi边缘stir的方法 |
CN109360805A (zh) * | 2018-09-28 | 2019-02-19 | 沈阳硅基科技有限公司 | 一种图形soi硅片的制备方法 |
FR3146019A1 (fr) * | 2023-02-16 | 2024-08-23 | Soitec | Procédé de formation d’une zone de fragisilation dans un substrat semi-conducteur |
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US20080315349A1 (en) * | 2005-02-28 | 2008-12-25 | Shin-Etsu Handotai Co., Ltd. | Method for Manufacturing Bonded Wafer and Bonded Wafer |
WO2012012138A2 (en) * | 2010-06-30 | 2012-01-26 | Corning Incorporated | Method for finishing silicon on insulator substrates |
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JPH0355822A (ja) | 1989-07-25 | 1991-03-11 | Shin Etsu Handotai Co Ltd | 半導体素子形成用基板の製造方法 |
JPH0680624B2 (ja) | 1990-02-28 | 1994-10-12 | 信越半導体株式会社 | 接合ウエーハの製造方法 |
JP3422225B2 (ja) | 1997-07-08 | 2003-06-30 | 三菱住友シリコン株式会社 | 貼り合わせ半導体基板及びその製造方法 |
JP3500063B2 (ja) * | 1998-04-23 | 2004-02-23 | 信越半導体株式会社 | 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ |
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JP4398934B2 (ja) * | 2005-02-28 | 2010-01-13 | 信越半導体株式会社 | Soiウエーハの製造方法 |
US7902039B2 (en) | 2006-11-30 | 2011-03-08 | Sumco Corporation | Method for manufacturing silicon wafer |
JP5233111B2 (ja) | 2006-11-30 | 2013-07-10 | 株式会社Sumco | 貼り合わせsoiウェーハの製造方法 |
JP2011187502A (ja) | 2010-03-04 | 2011-09-22 | Seiko Epson Corp | 半導体装置の製造方法 |
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US20070069335A1 (en) * | 2003-09-08 | 2007-03-29 | Akihiko Endo | Bonded wafer and its manufacturing method |
US20080315349A1 (en) * | 2005-02-28 | 2008-12-25 | Shin-Etsu Handotai Co., Ltd. | Method for Manufacturing Bonded Wafer and Bonded Wafer |
WO2012012138A2 (en) * | 2010-06-30 | 2012-01-26 | Corning Incorporated | Method for finishing silicon on insulator substrates |
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CN104620384A (zh) | 2015-05-13 |
KR20150087181A (ko) | 2015-07-29 |
WO2014080563A1 (ja) | 2014-05-30 |
JP2014103329A (ja) | 2014-06-05 |
EP2924736A4 (en) | 2016-06-29 |
US9378999B2 (en) | 2016-06-28 |
US20150243550A1 (en) | 2015-08-27 |
CN104620384B (zh) | 2017-06-06 |
EP2924736A1 (en) | 2015-09-30 |
EP2924736B1 (en) | 2017-08-30 |
JP5821828B2 (ja) | 2015-11-24 |
SG11201501873QA (en) | 2015-05-28 |
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