KR100966638B1 - Capacitor embedded printed circuit board and its manufacturing method - Google Patents

Abstract

Disclosed are a capacitor-embedded printed circuit board and a method of manufacturing the same. A core substrate; An insulating resin layer laminated on one surface of the core substrate; A first electrode and a first circuit pattern embedded in the insulating resin layer; A dielectric layer laminated on one surface of the insulating resin layer; A first adhesive resin layer laminated on the dielectric layer; And a capacitor embedded printed circuit board including a second electrode and a second circuit pattern formed on one surface of the first adhesive resin layer corresponding to the first electrode, which may simplify the manufacturing process and reduce the variation in capacitance (C). Can reduce the reliability of the product.

Capacitors, Printed Circuit Boards, Bonding, Roughness

Description

Printed circuit board having capacitor and manufacturing method

The present invention relates to a printed circuit board with a capacitor and a method of manufacturing the same.

BACKGROUND In recent years, various needs of consumers are increasing in electronic products including portable electronic devices. In particular, consumers' desire for multi-functionality, small size, light weight, low price, increased mobility, real-time contact with the Internet using wireless, and sleek design has placed a heavy burden on designers and manufacturers to make excellent products. As a result of this fierce competition, competitors are quickly releasing new models, which in turn adds to the burden on designers and manufacturers.

As the product's functions diversify, passive components also increase relative to the number of ICs, increasing the volume of portable terminals. In general, a large number of active and passive components are mounted on a circuit board in an electronic device, and a large number of passive components are mounted on a surface of a circuit board to facilitate signal transmission between active components in the form of discrete chip capacitors. do.

Embedded PCBs are being developed by many related companies for the high-density packaging of electronic systems. The passive components embedded in the board include L, R, and C. The separate chip-type passive components had limitations in meeting the trend of thin and short products, and there was a problem in terms of space utilization. It has a disadvantage.

There are several methods for implementing an embedded capacitor. Recently, there has been increasing interest in a method of implementing an embedded capacitor using a RCC type material having a relatively good thickness control, but the lamination of the RCC type material is very poor, thereby essentially flattening the surface on which the RCC type material is stacked. There is an additional process that must be done.

Structural problem of RCC type material is that despite the additional process of flattening the laminated surface, the dielectric thickness variation of the material greatly occurs with respect to the circuit pattern thickness or resin thickness of the laminated surface, and even in the laminated surface This leads to poor reliability such as delamination.

The present invention provides a substrate for a capacitor-embedded printed circuit board, a capacitor-embedded printed circuit board, and a manufacturing method thereof, which can simplify the manufacturing process and improve the reliability of the product by reducing the variation in capacitance (C).

According to an aspect of the invention, the dielectric layer; And a first adhesive resin layer laminated on one surface of the dielectric layer, and the first adhesive resin layer may provide a substrate for a capacitor-embedded printed circuit board, wherein roughness may be formed.

The second adhesive resin layer may be stacked on the other surface of the dielectric layer, and the second adhesive resin layer may be formed of a material capable of forming roughness. In this case, a first metal layer may be stacked on the first adhesive resin layer. In addition, a second metal layer may be stacked on the second adhesive resin layer.

According to another aspect of the invention, the core substrate; An insulating resin layer laminated on one surface of the core substrate; A first electrode and a first circuit pattern embedded in the insulating resin layer; A dielectric layer laminated on one surface of the insulating resin layer; A first adhesive resin layer laminated on the dielectric layer; And a second electrode and a second circuit pattern formed on one surface of the first adhesive resin layer corresponding to the first electrode.

The first adhesive resin layer may be a roughening process, and a second adhesive resin layer may be interposed between the insulating resin layer and the dielectric layer. In this case, the second adhesive resin layer may be a roughening treatment.

In addition, an insulating substrate may be stacked on the first adhesive resin layer to cover the second electrode, a third circuit pattern may be formed on one surface of the insulating substrate, and a via penetrating the insulating substrate may also be formed. .

According to still another aspect of the present invention, there is provided a substrate comprising a first metal layer, a dielectric layer, and an adhesive resin layer sequentially stacked; Etching a portion of the first metal layer to form a first electrode and a first circuit pattern; Pressing one surface of the substrate on which the first electrode is formed to the core substrate through the insulating resin layer; Forming a second electrode and a second circuit pattern on the adhesive resin layer; Stacking an insulating substrate on the substrate to cover the second electrode and the second circuit pattern; And it may provide a method for manufacturing a capacitor-embedded printed circuit board comprising the step of forming a third circuit pattern on the insulating substrate.

A second metal layer may be stacked on the adhesive resin layer, and the forming of the second electrode and the second circuit pattern may be performed by etching a portion of the second metal layer.

In addition, before the lamination of the insulating substrate, a step of performing a roughening process on the adhesive resin layer may be performed. In this case, the forming of the second electrode and the second circuit pattern may include forming a seed layer on the roughened adhesive resin layer; Forming a plating resist on the seed layer; Forming a plating layer corresponding to the second electrode and the second circuit pattern through electroplating; Removing the plating resist; And performing a flash etch so that a portion of the seed layer is removed.

Meanwhile, the forming of the second electrode and the second circuit pattern may be performed before the compressing step.

In addition, two substrates may be used to compress the substrates on both sides of the core substrate.

According to still another aspect of the present invention, there is provided a substrate comprising a first metal layer, a first adhesive resin layer, a dielectric layer, and a second adhesive resin layer sequentially stacked; Etching a portion of the first metal layer to form a first electrode and a first circuit pattern; Performing a roughening treatment on the first adhesive resin layer; Pressing one surface of the substrate on which the first electrode is formed to the core substrate through the insulating resin layer; Forming a second electrode and a second circuit pattern on the second adhesive resin layer; Stacking an insulating substrate on the substrate to cover the second electrode and the second circuit pattern; And it may provide a method for manufacturing a capacitor-embedded printed circuit board comprising the step of forming a third circuit pattern on the insulating substrate.

A second metal layer may be stacked on the second adhesive resin layer, and the forming of the second electrode and the second circuit pattern may be performed by etching a portion of the second metal layer.

Before the stacking of the insulating substrate, a roughening process may be performed on the second adhesive resin layer. In this case, the forming of the second electrode and the second circuit pattern may include forming the roughened second layer. Forming a seed layer on the adhesive resin layer; Forming a plating resist on the seed layer; Forming a plating layer corresponding to the second electrode and the second circuit pattern through electroplating; Removing the plating resist; And performing a flash etch so that a portion of the seed layer is removed.

The forming of the second electrode and the second circuit pattern may be performed before the compressing step. In addition, two substrates may be used to compress the substrates on both sides of the core substrate.

According to still another aspect of the present invention, there is provided a substrate comprising a first adhesive resin layer, a dielectric layer, and a second adhesive resin layer sequentially stacked; Performing a roughening treatment on the first adhesive resin layer; Forming a roughened first adhesive resin layer first electrode and a first circuit pattern through a plating process; Pressing one surface of the substrate on which the first electrode is formed to the core substrate through the insulating resin layer; Forming a second electrode and a second circuit pattern on the second adhesive resin layer; Stacking an insulating substrate on the substrate to cover the second electrode and the second circuit pattern; And it may provide a method for manufacturing a capacitor-embedded printed circuit board comprising the step of forming a third circuit pattern on the insulating substrate.

Before the stacking of the insulating substrate, a roughening process may be performed on the second adhesive resin layer, wherein the forming of the second electrode and the second circuit pattern may be performed through a plating process. .

In addition, the forming of the second electrode and the second circuit pattern may be performed before the pressing step, or the substrate may be pressed onto both surfaces of the core substrate using two substrates.

According to a preferred embodiment of the present invention, by forming the adhesive resin layer of the thin film on one or both sides of the dielectric layer, and forming the roughness as necessary, it is possible to simplify the manufacturing process, reducing the variation of capacitance (C) of the product It is possible to provide a method for manufacturing a printed circuit board with a capacitor that can improve reliability.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, a preferred embodiment of a capacitor-embedded printed circuit board and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings, and in the following description with reference to the accompanying drawings, the same or corresponding components are the same reference numerals. And duplicate description thereof will be omitted.

First, to describe the substrate for a capacitor-embedded printed circuit board according to an aspect of the present invention.

1 is a cross-sectional view showing a first embodiment of a substrate for a capacitor-embedded printed circuit board according to an aspect of the present invention, and FIG. 2 is a second embodiment of a substrate for a capacitor-embedded printed circuit board according to an aspect of the present invention. 3 is a cross-sectional view showing a third embodiment of a substrate for a capacitor-embedded printed circuit board according to an aspect of the present invention, and FIG. 4 is a cross-sectional view of a substrate for a capacitor-embedded printed circuit board according to an aspect of the present invention. It is sectional drawing which shows 4 Example. 1 to 4, dielectric layers 11, adhesive resin layers 12, 12a, 12b, and metal layers 13, 14 are shown.

The substrate according to the first embodiment has a structure in which the adhesive resin layer 12 is laminated on one surface of the dielectric layer 11, but the adhesive resin layer 12 is made of a material capable of forming roughness. In this case, the dielectric layer 11 may be in a semi-cured state (B-stage), or may be in a hardened state (C-stage).

In this case, the adhesive resin layer 12 stacked on the dielectric layer 11 may have a thickness of about several um. As described above, the adhesive resin layer 12 presented in this embodiment may be made of a material capable of forming roughness through a roughening treatment, for example, Korean Patent Publication No. 10-2007-0078086 (Applicant: Mitsubishi Gas Chemical Company And the adhesives mentioned in the patent. In addition to this, any material that can form roughness can be applied, of course.

Meanwhile, as shown in FIG. 2, the adhesive resin layers 12a and 12b may be formed on both sides of the dielectric layer, and as shown in FIG. 3, the metal layer 13 may be formed on one surface thereof. When the metal layer 13 is formed, there is no need to perform a separate metal layer stacking process to form a lower electrode or an upper electrode of the capacitor embedded in the printed circuit board, and the capacitor may be etched through the process of etching the metal layer. It is possible to easily form the electrode.

Although the metal layer may be formed on only one surface as shown in FIG. 3, the metal layers 13 and 14 may be formed on both sides of the dielectric layer 11 as shown in FIG. 4.

Next, a capacitor-embedded printed circuit board according to another aspect of the present invention will be described.

5 is a cross-sectional view showing a first embodiment of a capacitor-embedded printed circuit board according to another aspect of the present invention, and FIG. 6 is a cross-sectional view showing a second embodiment of a capacitor-embedded printed circuit board according to another aspect of the present invention. 5 and 6, the dielectric layer 11, the adhesive resin layer 12 ′, the first adhesive resin layer 12a ′, the second adhesive resin layer 12b ′, the first electrode 13a, The second electrode 14a, the first circuit pattern 13b, the second circuit pattern 14b, the core substrate 20, the insulating resin layer 21, the insulating substrate 31, the vias 32 and 33, and the third Circuit pattern 34 and solder resist 35 are shown.

In the case of the printed circuit board as shown in FIG. 5, the first electrode 13a, the dielectric layer 11, the adhesive resin layer 12 ′, and the second electrode 14a may implement a patterned capacitor. do.

Capacitor-embedded printed circuit board having such a structure can minimize the possibility of delamination that may occur at the part where the insulating substrate 31 is laminated by the adhesive resin layer 12 'having the roughness. It can improve the reliability.

Further, the adhesive resin layer 12 'may be thinned (within a few um) to minimize the influence that the adhesive resin layer 12' may have on the performance of the capacitor.

Although the adhesive resin layer 12 'is formed on only one side of the dielectric layer 11 in FIG. 5, the adhesive resin layers 12a' and 12b 'are formed on both surfaces of the dielectric layer 11 as shown in FIG. Of course, it can also be formed.

Hereinafter, a method of manufacturing a printed circuit board having the above-described structure will be described in more detail.

7 is a flow chart showing a first embodiment of a method for manufacturing a capacitor-embedded printed circuit board according to another aspect of the present invention, and FIGS. 8 to 19 are cross-sectional views illustrating respective processes of the manufacturing method of FIG. 7. 8 to 19, the dielectric layer 11, the adhesive resin layers 12 and 12 ′, the metal layer 13, the first electrode 13a, the first circuit pattern 13b, and the second electrode 14a. The second circuit pattern 14b, the seed layer 16, the plating resist 17, the core layer 20, the insulating resin layer 21, the insulating substrate 31, the vias 32 and 33, and the third circuit. The pattern 34, etch resist 35 is shown.

First, as shown in FIG. 8, a substrate in which a metal layer 13, a dielectric layer 11, and an adhesive resin layer 12 are sequentially stacked is provided (S110). The adhesive resin layer 12 may not only improve the bonding strength between the dielectric layer 11 and the metal layer 13, but also improve the bonding strength with the insulating substrate 31, which will be described later, thereby improving reliability of the product. Can be performed.

In this case, the adhesive resin layer 12 may be formed in the form of a thin film to minimize the influence on the capacitance of the capacitor embedded in the substrate. For example, the thickness of the adhesive resin layer 12 may be less than 10um.

Next, as shown in FIG. 9, a portion of the metal layer 13 is etched to form the first electrode 13a and the first circuit pattern 13b (S120). The first electrode 13a is to function as an upper electrode or a lower electrode of the capacitor embedded in the printed circuit board according to the present embodiment, and the position, size, etc. of the capacitor may be variously changed according to the intention of the designer. have.

10 and 11, one surface of the substrate on which the first electrode 13a is formed is pressed onto the core substrate 20 through the insulating resin layer 21 (S130). At this time, two substrates may be prepared and then pressed against both surfaces of the core substrate 20. Through this process, a multi-layer structure can be realized.

Next, as shown in FIG. 12, a roughening process may be performed on the adhesive resin layer 12 (S140). By forming roughness in the adhesive resin layer 12 through the roughening process, the seed layer 16 to be described later can be more firmly formed on the adhesive resin layer 12. Reference numeral 12 ′ in FIG. 12 denotes an adhesive resin layer having roughness formed.

After the roughening treatment is performed, the second electrode 14a and the second circuit pattern 14b are formed on the adhesive resin layer 12 '(S150). In addition to the first electrode 13a described above, the second electrode 14a may implement a capacitor embedded in a printed circuit board. When the first electrode 13a is a lower electrode, the second electrode 14a is an upper electrode. Can be. Therefore, the second electrode 14a may be formed in consideration of the position and size of the first electrode 13a. A method of forming the second electrode 14a and the second circuit pattern 14b will be described in more detail as follows.

First, as illustrated in FIG. 13, the seed layer 16 is formed on the roughened adhesive resin layer 12 ′ (S151). As a method of forming the seed layer 16, sputtering system may be used and other electroless plating system may be used.

Then, as shown in FIG. 14, the plating resist 17 is formed on the seed layer 16 (S152). In order to form the plating resist 17, a method of stacking a dry film (not shown) on the seed layer 16 and then exposing / developing may be used. In addition, the plating resist 17 may be formed through various methods.

Next, as shown in FIG. 15, a plating layer corresponding to the second electrode 14a and the second circuit pattern 14b is formed through electroplating (S153), and as shown in FIG. After removing (17) (S154), as shown in FIG. 17, flash etching is performed to remove a part of the seed layer 16, thereby forming the pattern of the second electrode 14a and the second circuit pattern 14b. It is possible to finish the anger (S155).

As such, when the second electrode 14a is formed using the plating method, an electrode having a more accurate size can be formed, and thus the capacitance of the capacitor can be more accurately adjusted.

After forming the second electrode 14a and the second circuit pattern 14b through the above process, the insulating substrate 31 is laminated on the substrate to cover the second electrode 14a and the second circuit pattern 14b. In operation S160, the third circuit pattern 34 may be formed on the insulating substrate 31 (S170).

In addition to the third circuit pattern 34, vias 32 and 33 may be formed for interlayer conduction, and a solder resist 35 may be formed on the outermost side of the third circuit pattern 34 to protect the third circuit pattern 34.

Meanwhile, in the present embodiment, the substrate on which the first electrode 13a and the first circuit pattern 13b are formed is laminated on the core substrate 20, and then the second electrode 14a and the second circuit pattern 14b are formed. 19, the first electrode 13a, the first circuit pattern 13b, the second electrode 14a, and the second circuit pattern 14b are formed on the substrate. Next, it may be laminated on the core substrate 20.

Next, a second embodiment will be described.

20 is a flow chart showing a second embodiment of a method for manufacturing a capacitor-embedded printed circuit board according to another aspect of the present invention, and FIGS. 21 to 28 are cross-sectional views illustrating respective processes of the manufacturing method of FIG. 20. 21 to 28, the dielectric layer 11, the adhesive resin layers 12 and 12 ′, the first metal layer 13, the first electrode 13a, the first circuit pattern 13b, and the second metal layer ( 14, the second electrode 14a, the second circuit pattern 14b, the core layer 20, the insulation resin layer 21, the insulation substrate 31, the vias 32 and 33, and the third circuit pattern 34. ), An etching resist 35 is shown.

This embodiment differs from the first embodiment described above in that the second electrode 14a and the second circuit pattern 14b are formed by an etching method rather than a plating method. Hereinafter, the present embodiment will be described based on these differences, and a description of the corresponding parts will be omitted.

First, as shown in FIG. 21, a substrate in which the first metal layer 13, the dielectric layer 11, the adhesive resin layer 12, and the second metal layer 14 are sequentially stacked is provided (S210). As described above, in the present embodiment, since the second electrode 14a and the second circuit pattern 14b are formed by an etching method, the substrate on which the second metal layer 14 is laminated on the adhesive resin layer 12 is formed. It is to use.

Then, as shown in FIG. 22, a portion of the first metal layer 13 is etched to form the first electrode 13a and the first circuit pattern 13b (S220), and FIGS. 23 and 24. As shown, one surface of the substrate on which the first electrode 13a is formed is pressed onto the core substrate 20 through the insulating resin layer 21 (S230).

Next, as shown in FIG. 25, a portion of the second metal layer 14 is etched to form the second electrode 14a and the second circuit pattern 14b (S240). The second electrode 14a may implement a capacitor in addition to the first electrode 13a described above, and when the first electrode 13a is a lower electrode, the second electrode 14a may be an upper electrode. Therefore, the second electrode 14a may be formed in consideration of the position and size of the first electrode 13a.

Then, as shown in FIG. 26, a desmear treatment may be performed on the adhesive resin layer 12 (S250). By etching a part of the second metal layer 14 stacked on the adhesive resin layer 12, a part of the adhesive resin layer 12 may be exposed to the outside, thereby forming roughness on the exposed surface. . By forming the roughness in the adhesive resin layer 12, it is possible to improve the bonding force with the insulating substrate 31 to be laminated later, as a result it is possible to reduce the risk of delamination to improve the reliability of the product You can do it. Reference numeral 12 ′ in FIG. 26 denotes an adhesive resin layer on which roughness is formed.

Next, as shown in FIG. 27, an insulating substrate 31 is laminated on the substrate to cover the second electrode 14a and the second circuit pattern 14b (S260), and the third substrate is stacked on the insulating substrate 31. The circuit pattern 34 may be formed (S270). In addition to the third circuit pattern 34, vias 32 and 33 may be formed for interlayer conduction, and a solder resist 35 may be formed on the outermost side of the third circuit pattern 34 to protect the third circuit pattern 34.

Meanwhile, in the present embodiment, the substrate on which the first electrode 13a and the first circuit pattern 13b are formed is laminated on the core substrate 20, and then the second electrode 14a and the second circuit pattern 14b are formed. 28, the first electrode 13a, the first circuit pattern 13b, the second electrode 14a, and the second circuit pattern 14b are formed on the substrate. Next, it may be laminated on the core substrate 20.

Next, a third embodiment will be described.

29 is a flowchart illustrating a third embodiment of a method for manufacturing a capacitor-embedded printed circuit board according to another exemplary embodiment of the present invention, and FIGS. 30 to 42 are cross-sectional views illustrating respective processes of the manufacturing method of FIG. 29. 30 to 42, the dielectric layer 11, the first adhesive resin layers 12a and 12a ', the second adhesive resin layers 12b and 12b', the metal layer 13, the first electrode 13a, First circuit pattern 13b, second electrode 14a, second circuit pattern 14b, seed layer 16, plating resist 17, core layer 20, insulating resin layer 21, insulating substrate 31, vias 32 and 33, third circuit pattern 34, and etching resist 35 are shown.

The manufacturing method according to the present embodiment has a difference in that adhesive resin layers 12a and 12b are formed on both surfaces of the dielectric layer 11 as compared with the first embodiment described above. Hereinafter, the present embodiment will be described based on these differences, and detailed descriptions of the same or corresponding parts will be omitted.

First, as shown in FIG. 30, a substrate in which the first metal layer 13, the first adhesive resin layer 12a, the dielectric layer 11, and the second adhesive resin layer 12b are sequentially stacked is provided. (S310).

Then, as shown in FIG. 31, a portion of the first metal layer 13 is etched to form the first electrode 13a and the first circuit pattern 13b (S320), and as shown in FIG. 32. Likewise, a roughening treatment is performed on the first adhesive resin layer 12a (S330).

By etching a part of the first metal layer 13 stacked on the first adhesive resin layer 12a, a part of the first adhesive resin layer 12a may be exposed to the outside, and thus the roughness of the exposed surface may be exposed. To form. By forming roughness in the first adhesive resin layer 12a, it is possible to improve the bonding force with the insulating substrate 31 to be laminated later, and as a result, it is possible to reduce the risk of delamination, resulting in reliability of the product. It will be possible to improve.

Then, as illustrated in FIGS. 33 and 34, one surface of the substrate on which the first electrode 13a is formed is pressed onto the core substrate 20 via the insulating resin layer 21 (S340). At this time, two substrates may be prepared and then pressed against both surfaces of the core substrate 20. Through this process, a multi-layer structure can be realized.

Next, as shown in FIG. 35, a roughening process is performed on the second adhesive resin layer 12b (S350). By forming roughness in the second adhesive resin layer 12b through the roughening treatment, the seed layer 16 to be described later can be more firmly formed on the second adhesive resin layer. Reference numeral 12b 'of FIG. 35 denotes a second adhesive resin layer having roughness formed.

After the roughening treatment is performed, the second electrode 14a and the second circuit pattern 14b are formed on the second adhesive resin layer 12b (S360). To this end, as shown in FIG. 36, the seed layer 16 is formed on the roughened second adhesive resin layer 12b ′ (S361), and as shown in FIG. 37, the seed layer 16. After forming the plating resist 17 on the (S362), as shown in Figure 38, through the electroplating to form a plating layer corresponding to the second electrode 14a and the second circuit pattern 14b ( S363), as shown in FIG. 39, after removing the plating resist 17 (S364), as shown in FIG. 40, flash etching may be performed to remove a portion of the seed layer 16. As in the case of the first embodiment (S365).

Next, as shown in FIG. 41, an insulating substrate 31 is laminated on the substrate to cover the second electrode 14a and the second circuit pattern 14b (S370), and the third substrate is stacked on the insulating substrate 31. The circuit pattern 34 may be formed (S380).

Meanwhile, in the present embodiment, the substrate on which the first electrode 13a and the first circuit pattern 13b are formed is laminated on the core substrate 20, and then the second electrode 14a and the second circuit pattern 14b are formed. As shown in FIG. 42, the first electrode 13a, the first circuit pattern 13b, the second electrode 14a, and the second circuit pattern 14b are formed on the substrate. Next, it may be laminated on the core substrate 20.

Next, a fourth embodiment will be described.

43 is a flowchart illustrating a fourth embodiment of a method for manufacturing a capacitor-embedded printed circuit board according to another exemplary embodiment of the present invention, and FIGS. 44 to 52 are cross-sectional views illustrating respective processes of the manufacturing method of FIG. 43. 44 to 52, the dielectric layer 11, the first adhesive resin layers 12a and 12a ', the second adhesive resin layers 12b and 12b', the first metal layer 13, and the first electrode 13a ), The first circuit pattern 13b, the second metal layer 14, the second electrode 14a, the second circuit pattern 14b, the core layer 20, the insulating resin layer 21, and the insulating substrate 31. , Vias 32 and 33, third circuit pattern 34, and etching resist 35 are shown.

This embodiment differs from the third embodiment in that the second electrode 14a and the second circuit pattern 14b are formed by an etching method rather than a plating method. Hereinafter, the present embodiment will be described based on these differences, and a description of the corresponding parts will be omitted.

First, as shown in FIG. 44, the first metal layer 13, the first adhesive resin layer 12a, the dielectric layer 11, the second adhesive resin layer 12b, and the second metal layer 14. The substrate laminated in this order is provided (S410). As described above, in the present embodiment, since the second electrode 14a and the second circuit pattern 14b are formed by an etching method, the second metal layer 14 is stacked on the second adhesive resin layer 12b. It uses a base material.

Then, as shown in FIG. 45, a portion of the first metal layer 13 is etched to form the first electrode 13a and the first circuit pattern 13b (S420), and as shown in FIG. 46. Likewise, a roughening treatment is performed on the first adhesive resin layer 12a (S430).

When a part of the first metal layer 13 that is stacked on the first adhesive resin layer 12a is etched, a part of the first adhesive resin layer 12a may be exposed to the outside. To form. By forming roughness in the first adhesive resin layer 12a, it is possible to improve the bonding strength with the insulating substrate 31 to be laminated later, and as a result, it is possible to reduce the risk of delamination occurs. It is possible to improve the reliability. Reference numeral 12a 'in FIG. 46 denotes a first adhesive resin layer on which roughness is formed.

47 and 48, one surface of the substrate on which the first electrode 13a is formed via the insulating resin layer 21 is pressed onto the core substrate 20 (S440), and FIG. 49. As shown, after etching a portion of the second metal layer 14 to form the second electrode 14a and the second circuit pattern 14b (S450), as shown in FIG. 50, the second adhesive water A roughening process is also performed on the strata 12b (S460). Reference numeral 12b 'of FIG. 50 denotes a second adhesive resin layer having roughness formed.

Then, as illustrated in FIG. 51, an insulating substrate 31 is laminated on the substrate to cover the second electrode 14a and the second circuit pattern 14b (S470), and the third substrate is stacked on the insulating substrate 31. The circuit pattern 34 may be formed (S480). In addition to the third circuit pattern 34, vias 32 and 33 may be formed for interlayer conduction, and a solder resist 35 may be formed on the outermost side of the third circuit pattern 34 to protect the third circuit pattern 34.

Meanwhile, in the present embodiment, the substrate on which the first electrode 13a and the first circuit pattern 13b are formed is laminated on the core substrate 20, and then the second electrode 14a and the second circuit pattern 14b are formed. As shown in FIG. 52, the first electrode 13a, the first circuit pattern 13b, the second electrode 14a, and the second circuit pattern 14b are formed on the substrate. Next, it may be laminated on the core substrate 20.

Next, a fifth embodiment will be described.

53 is a flowchart illustrating a fifth embodiment of a method for manufacturing a capacitor-embedded printed circuit board according to another aspect of the present invention, and FIGS. 54 to 66 are cross-sectional views illustrating respective processes of the manufacturing method of FIG. 53. 54 to 66, the dielectric layer 11, the first adhesive resin layers 12a and 12a ', the second adhesive resin layers 12b and 12b', the first electrode 13a and the first circuit pattern ( 13b), second electrode 14a, second circuit pattern 14b, seed layer 16, plating resist 17, core layer 20, insulating resin layer 21, insulating substrate 31, via 32, 33, a third circuit pattern 34, and an etching resist 35 are shown.

Unlike the above-described embodiments, the present embodiment forms the first electrode 13a, the first circuit pattern 13b, the second electrode 14a, and the second circuit pattern 14b by plating. There is a difference. Hereinafter, the present embodiment will be described based on these differences, and a description of the corresponding parts will be omitted.

First, as shown in FIG. 54, a substrate in which the first adhesive resin layer 12a, the dielectric layer 11, and the second adhesive resin layer 12b are sequentially stacked is provided (S510).

Then, as illustrated in FIG. 55, the first adhesive resin layer 12a is subjected to a roughening process (S520), and the roughened first adhesive resin layer 12a 'is subjected to a plating process. The first electrode 13a and the first circuit pattern 13b are formed at step S530. That is, as shown through the above-described embodiment, the first electrode 13a and the first circuit pattern 13b may be formed using the seed layer 16, the plating resist 17, or the like. This process is illustrated in FIGS. 56-60.

61 and 62, one surface of the substrate on which the first electrode 13a is formed is pressed onto the core substrate 20 via the insulating resin layer 21 (S540).

Then, as shown in FIG. 63, the second adhesive resin layer 12b is subjected to a roughening process (S550), and the roughened second adhesive resin layer 12b 'is subjected to a plating process. The second electrode 14a and the second circuit pattern 14b are formed (S560). Since the method of forming the second electrode 14a and the second circuit pattern 14b is the same as the method of forming the first electrode 13a and the first circuit pattern 13b, a detailed description thereof will be omitted. . 64 is a view showing the formation of the second electrode 14a and the second circuit pattern 14b.

After that, as shown in FIG. 65, the insulating substrate 31 is laminated on the substrate to cover the second electrode 14a and the second circuit pattern 14b (S570), and the third substrate is stacked on the insulating substrate 31. The circuit pattern 34 may be formed as in the above-described embodiments (S580).

Meanwhile, in the present embodiment, the substrate on which the first electrode 13a and the first circuit pattern 13b are formed is laminated on the core substrate 20, and then the second electrode 14a and the second circuit pattern 14b are formed. 66, the first electrode 13a, the first circuit pattern 13b, the second electrode 14a, and the second circuit pattern 14b are formed on the substrate. Next, it may be laminated on the core substrate 20.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

1 is a cross-sectional view showing a first embodiment of a substrate for a printed circuit board with a capacitor according to an aspect of the present invention.

Figure 2 is a cross-sectional view showing a second embodiment of a substrate for a capacitor-embedded printed circuit board according to an aspect of the present invention.

Figure 3 is a cross-sectional view showing a third embodiment of a substrate for a printed circuit board with a capacitor according to an aspect of the present invention.

Figure 4 is a cross-sectional view showing a fourth embodiment of a substrate for a capacitor-embedded printed circuit board according to an aspect of the present invention.

5 is a sectional view showing a first embodiment of a printed circuit board with a capacitor according to another aspect of the present invention.

Figure 6 is a cross-sectional view showing a second embodiment of a printed circuit board with a capacitor according to another aspect of the present invention.

Figure 7 is a flow chart showing a first embodiment of a method for manufacturing a capacitor-embedded printed circuit board according to another aspect of the present invention.

8-19 is sectional drawing which shows each process of the manufacturing method of FIG.

20 is a flow chart illustrating a second embodiment of a method for manufacturing a capacitor-embedded printed circuit board according to another aspect of the present invention.

21 to 28 are sectional views showing respective steps of the manufacturing method of FIG. 20.

29 is a flow chart showing a third embodiment of a method for manufacturing a capacitor-embedded printed circuit board according to another aspect of the present invention.

30-42 is sectional drawing which shows each process of the manufacturing method of FIG.

43 is a flowchart illustrating a fourth embodiment of a method for manufacturing a capacitor-embedded printed circuit board according to another aspect of the present invention.

44 to 52 are cross-sectional views illustrating each step of the manufacturing method of FIG. 43.

53 is a flow chart showing a fifth embodiment of a method for manufacturing a capacitor-embedded printed circuit board according to another aspect of the present invention.

54 to 66 are cross-sectional views illustrating respective steps of the manufacturing method of FIG. 53.

<Description of the symbols for the main parts of the drawings>

11: dielectric layer

12, 12 ', 12a, 12a', 12b, 12b ': adhesive resin layer

13, 14 metal layer 13a, 14a: electrode

13b and 14b: Circuit pattern 16: seed layer

17: plating resist 20: core substrate

21: insulating resin layer 31: insulating substrate

32, 33: Via 34: Circuit pattern

35: solder resist

Claims (25)

delete delete delete delete A core substrate; An insulating resin layer laminated on one surface of the core substrate; A first electrode and a first circuit pattern embedded in the insulating resin layer; A dielectric layer laminated on one surface of the insulating resin layer; A first adhesive resin layer laminated on the dielectric layer; And And a second electrode and a second circuit pattern formed on one surface of the first adhesive resin layer corresponding to the first electrode. The method of claim 5, The first adhesive resin layer is a capacitor-embedded printed circuit board, characterized in that the roughening (desmear) process was performed. The method of claim 5, And a second adhesive resin layer interposed between the insulating resin layer and the dielectric layer. The method of claim 7, wherein The second adhesive resin layer is a capacitor-embedded printed circuit board, characterized in that the roughening (desmear) process was performed. The method of claim 5, An insulating substrate stacked on the first adhesive resin layer to cover the second electrode; A third circuit pattern formed on one surface of the insulating substrate; And The printed circuit board with a capacitor further comprising a via penetrating the insulating substrate. Providing a substrate on which a first metal layer, a dielectric layer, and an adhesive resin layer are sequentially stacked; Etching a portion of the first metal layer to form a first electrode and a first circuit pattern; Pressing one surface of the substrate on which the first electrode is formed to the core substrate through the insulating resin layer; Forming a second electrode and a second circuit pattern on the adhesive resin layer; Stacking an insulating substrate on the substrate to cover the second electrode and the second circuit pattern; And And a third circuit pattern formed on the insulating substrate. The method of claim 10, A second metal layer is laminated on the adhesive resin layer, Forming the second electrode and the second circuit pattern, The method of manufacturing a printed circuit board with a capacitor, characterized in that performed by etching a portion of the second metal layer. The method of claim 10, Before stacking the insulating substrate, The method of manufacturing a capacitor-embedded printed circuit board further comprising a step of roughening the adhesive resin layer. The method of claim 12, Forming the second electrode and the second circuit pattern, Forming a seed layer on the roughened adhesive resin layer; Forming a plating resist on the seed layer; Forming a plating layer corresponding to the second electrode and the second circuit pattern through electroplating; Removing the plating resist; And And performing a flash etch so that a portion of the seed layer is removed. The method of claim 10, Forming the second electrode and the second circuit pattern, Method of manufacturing a capacitor-embedded printed circuit board, characterized in that performed before the pressing step. The method of claim 10, There are two said substrates, The pressing step is a capacitor embedded printed circuit board manufacturing method, characterized in that performed on both sides of the core substrate. Providing a substrate on which a first metal layer, a first adhesive resin layer, a dielectric layer, and a second adhesive resin layer are sequentially stacked; Etching a portion of the first metal layer to form a first electrode and a first circuit pattern; Performing a roughening treatment on the first adhesive resin layer; Pressing one surface of the substrate on which the first electrode is formed to the core substrate through the insulating resin layer; Forming a second electrode and a second circuit pattern on the second adhesive resin layer; Stacking an insulating substrate on the substrate to cover the second electrode and the second circuit pattern; And And a third circuit pattern formed on the insulating substrate. The method of claim 16, A second metal layer is laminated on the second adhesive resin layer, Forming the second electrode and the second circuit pattern, The method of manufacturing a printed circuit board with a capacitor, characterized in that performed by etching a portion of the second metal layer. The method of claim 16, Before stacking the insulating substrate, The method of manufacturing a capacitor-embedded printed circuit board further comprising performing a roughening process on the second adhesive resin layer. The method of claim 18, Forming the second electrode and the second circuit pattern, Forming a seed layer on the roughened second adhesive resin layer; Forming a plating resist on the seed layer; Forming a plating layer corresponding to the second electrode and the second circuit pattern through electroplating; Removing the plating resist; And And performing a flash etch so that a portion of the seed layer is removed. The method of claim 16, Forming the second electrode and the second circuit pattern, Method of manufacturing a capacitor-embedded printed circuit board, characterized in that performed before the pressing step. The method of claim 16, There are two said substrates, The pressing step is a capacitor embedded printed circuit board manufacturing method, characterized in that performed on both sides of the core substrate. Providing a substrate on which a first adhesive resin layer, a dielectric layer, and a second adhesive resin layer are sequentially stacked; Performing a roughening treatment on the first adhesive resin layer; Forming the first adhesive resin layer first electrode and the first circuit pattern roughened through a plating process; Pressing one surface of the substrate on which the first electrode is formed to the core substrate through the insulating resin layer; Forming a second electrode and a second circuit pattern on the second adhesive resin layer; Stacking an insulating substrate on the substrate to cover the second electrode and the second circuit pattern; And And a third circuit pattern formed on the insulating substrate. The method of claim 22, And performing a desmear treatment on the second adhesive resin layer before laminating the insulating substrate, Forming the second electrode and the second circuit pattern is a capacitor embedded printed circuit board manufacturing method, characterized in that performed through the plating process. The method of claim 22, Forming the second electrode and the second circuit pattern, Method of manufacturing a capacitor-embedded printed circuit board, characterized in that performed before the pressing step. The method of claim 22, There are two said substrates, The pressing step is a capacitor embedded printed circuit board manufacturing method, characterized in that performed on both sides of the core substrate.

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