[go: up one dir, main page]

JP2008282953A - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

Info

Publication number
JP2008282953A
JP2008282953A JP2007125400A JP2007125400A JP2008282953A JP 2008282953 A JP2008282953 A JP 2008282953A JP 2007125400 A JP2007125400 A JP 2007125400A JP 2007125400 A JP2007125400 A JP 2007125400A JP 2008282953 A JP2008282953 A JP 2008282953A
Authority
JP
Japan
Prior art keywords
wiring board
electronic component
manufacturing
stopper material
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007125400A
Other languages
Japanese (ja)
Inventor
Hidekatsu Sekine
秀克 関根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP2007125400A priority Critical patent/JP2008282953A/en
Publication of JP2008282953A publication Critical patent/JP2008282953A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a wiring board which shortens the connection between a built-in semiconductor element and an upper layer and further, can contain a cheap chip component of general goods on the market whose electrode is formed with tin, nickel and copper, and a low-cost semiconductor element with a bump, such as, a copper bump also. <P>SOLUTION: In the wiring board 1 packaging electronic components of a semiconductor element 3 and a chip component 4, a stopper material 2 for an etchant is formed on a copper foil, at a position corresponding to an electrode of the electronic component; and after the electronic components are packaged, they are laminated through an insulating layer 5. Further, after the copper foil is removed by etching, a wiring is formed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は各種電子機器の配線基板の製造方法に係わり、さらに詳しくは半導体素子等の電子部品が内蔵される配線基板の製造方法に関するものである。   The present invention relates to a method for manufacturing a wiring board for various electronic devices, and more particularly to a method for manufacturing a wiring board in which electronic components such as semiconductor elements are incorporated.

電子部品の高密度実装が可能な配線基板として、特許文献１に、内部に空孔を設け該空孔に半導体チップを内蔵する配線基板が提案されている。これら電子部品が内蔵される配線基板の第一の製造方法を、図５（ａ）及び（ｂ）に示す。配線基板の途中工程である基板１５の配線８上に、半導体素子３のフリップチップ実装を行い、チップ部品４の半田接続実装を行う（図示せず）。次に、基板表面を絶縁層及び銅箔で順次覆い、銅箔を除去後、レーザー等でビア穴を形成し、更にその絶縁層上に導体層を形成し、配線８を形成するといった工程を行い、電子部品を内蔵している。   As a wiring board capable of high-density mounting of electronic components, Patent Document 1 proposes a wiring board in which a hole is provided and a semiconductor chip is built in the hole. 5A and 5B show a first method for manufacturing a wiring board in which these electronic components are built. Flip chip mounting of the semiconductor element 3 is performed on the wiring 8 of the substrate 15 which is an intermediate step of the wiring substrate, and solder connection mounting of the chip component 4 is performed (not shown). Next, a process of sequentially covering the substrate surface with an insulating layer and copper foil, removing the copper foil, forming a via hole with a laser or the like, further forming a conductor layer on the insulating layer, and forming the wiring 8 is performed. Do and have built-in electronic components.

ここで、配線基板に内蔵される半導体素子等の電子部品の形態は、接続用として電極上に金バンプや銅バンプが形成された半導体素子や、外装がスズや銅等で形成された電極であるキャパシタや抵抗体等のチップ部品である。   Here, the form of an electronic component such as a semiconductor element incorporated in the wiring board is a semiconductor element in which gold bumps or copper bumps are formed on electrodes for connection, or an electrode in which the exterior is formed of tin, copper, or the like. A chip component such as a capacitor or resistor.

また、第２の製造方法としては、図６（ａ）に示すように、まず、半導体素子３やチップ部品４を配線基板の途中工程である基板１５上に接着させる。更に、図６（ｂ）に示すように、基板表面を絶縁層５及び銅箔１０１で覆うといった積層工程を行う。次いで、図６（ｃ）に示すように、銅箔１０１を除去後、レーザーにて、半導体素子３上のバンプ表面やチップ部品４の電極表面を露出させ、またビア穴１６を形成する。次いで、無電解めっき及び電解めっきを行うことで、上層と内蔵された電子部品を接続するビア１４を形成し、次いで、上層の配線８を形成することにより、図６（ｄ）に示すように電子部品を内蔵する方法が、特許文献２に公開されている。   As a second manufacturing method, as shown in FIG. 6A, first, the semiconductor element 3 and the chip component 4 are bonded onto the substrate 15 which is an intermediate step of the wiring substrate. Further, as shown in FIG. 6B, a lamination process is performed in which the substrate surface is covered with the insulating layer 5 and the copper foil 101. Next, as shown in FIG. 6C, after removing the copper foil 101, the bump surface on the semiconductor element 3 and the electrode surface of the chip component 4 are exposed with a laser, and the via hole 16 is formed. Next, by performing electroless plating and electrolytic plating, a via 14 is formed to connect the upper layer and the built-in electronic component, and then an upper layer wiring 8 is formed, as shown in FIG. A method of incorporating an electronic component is disclosed in Patent Document 2.

第３の製造方法としては、図７（ａ）に示すように、金バンプ付半導体素子３及び金バンプ付チップ部品４を、銅箔１０１に絶縁樹脂や非導電性接着剤１８NCＦ（Non-conductive Film）等の接着剤１０を介して接着させ、実装基板１１を作製する。次いで、図７（ｂ）に示すように、途中工程である基板１５上に絶縁層５を介して実装基板11の積層工程を行う。次いで、銅箔１０１をエッチングにて除去することにより、図７（ｃ）に示すように、半導体素子３及びチップ部品４上のバンプ表面を露出させる。次いで、図７（ｄ）に示すように、ビア穴１６を形成し、無電解めっき及び電解めっきを行うことで、導体層７及びビア１４を形成する。次いで、上層の配線８をエッチング形成することにより図７（ｅ）に示すように、電子部品を内蔵する方法が、特許文献３に公開されている。   As a third manufacturing method, as shown in FIG. 7A, a semiconductor element 3 with gold bumps and a chip part 4 with gold bumps are bonded to a copper foil 101 with an insulating resin or a non-conductive adhesive 18NCF (Non-conductive). The mounting substrate 11 is manufactured by bonding through an adhesive 10 such as a film. Next, as illustrated in FIG. 7B, the mounting substrate 11 is laminated on the substrate 15, which is an intermediate step, via the insulating layer 5. Next, the copper foil 101 is removed by etching, so that the bump surfaces on the semiconductor element 3 and the chip component 4 are exposed as shown in FIG. Next, as shown in FIG. 7D, via holes 16 are formed, and electroless plating and electrolytic plating are performed to form the conductor layer 7 and the vias 14. Next, as shown in FIG. 7E, a method of incorporating an electronic component by etching the upper wiring 8 is disclosed in Patent Document 3.

しかしながら、第１の製造方法の場合、上層との接続を図る際、全て、半導体素子およびチップ部品の実装面から放射状に長い配線を形成し、上層とビアで導通を図る必要がある為、配線基板が大きくなるといった問題や、配線設計の自由度が小さいといった問題、更には他の部品接続の配線長が長くなるため電気的特性が悪いといった問題がある。   However, in the case of the first manufacturing method, when connecting with the upper layer, it is necessary to form a long wiring radially from the mounting surface of the semiconductor element and the chip component, and to connect the upper layer with the via. There is a problem that the board becomes large, a problem that the degree of freedom in wiring design is small, and a problem that electrical characteristics are poor because the wiring length of other component connection becomes long.

また、第２の製造方法の場合、半導体素子の種類、また、チップ部品の種類によってビア穴の深さが異なるため、レーザーの焦点、パルスのエネルギー、ショット数等を複数条件設定することになる他、各レーザー条件設定に対応して配線基板への複数回の加工が必要となり、ビア穴加工の生産性が悪くなるといった問題がある。更に、半導体素子の場合は、近年、バンプ径が小さくなっているため、レーザー加工の位置ズレにより、半導体素子上の配線等を破壊してしまうといった問題もある。   In the case of the second manufacturing method, since the depth of the via hole differs depending on the type of the semiconductor element and the type of the chip component, a plurality of conditions such as the laser focus, the pulse energy, and the number of shots are set. In addition, there is a problem that the wiring board needs to be processed a plurality of times corresponding to each laser condition setting, and the productivity of via hole processing is deteriorated. Furthermore, in the case of a semiconductor element, since the bump diameter has been reduced in recent years, there is also a problem that the wiring on the semiconductor element is destroyed due to a positional shift of laser processing.

また、第３の製造方法においては、半導体素子と同時に、又は、単独で、チップ部品を内蔵する場合、市販品のチップ部品の電極は、スズ、ニッケル、銅で形成されたものであり、エッチング液に腐食されてしまう。この為、特注として、金めっき等のエッチング液に耐腐食性のあるめっきを施す、あるいは金バンプ等を電極上に設ける等の新しい技術が必要となり、また、チップ部品自体も高価なものとなるといった問題があった。
特開平６−４５７６３号公報 特開２００５−３３２８８７号公報 特開２００６−４９７６２号公報 特開２００５−１５９２２６号公報 Further, in the third manufacturing method, when the chip component is embedded simultaneously with the semiconductor element or independently, the electrode of the commercially available chip component is formed of tin, nickel, copper, and etched. Corroded by liquid. For this reason, as a special order, a new technique such as plating with corrosion resistance in an etching solution such as gold plating, or providing a gold bump or the like on the electrode is required, and the chip component itself becomes expensive. There was a problem.
JP-A-6-45763 JP 2005-332887 A JP 2006-49762 A JP 2005-159226 A

本発明は、前記問題点を鑑みなされたものであり、その目的とするところは、内蔵された半導体素子と上層との接続を短くし、更に電極がスズ、ニッケル、銅で形成された一般市販品の安価なチップ部品および、銅バンプ等の安価なバンプ付半導体素子までも内蔵可能な配線基板の製造方法を提供することにある。   The present invention has been made in view of the above-mentioned problems, and its object is to shorten the connection between the built-in semiconductor element and the upper layer, and furthermore, a general commercially available electrode in which the electrode is formed of tin, nickel, or copper. It is an object of the present invention to provide a method for manufacturing a wiring board that can be embedded even with inexpensive chip components and low-cost bumped semiconductor elements such as copper bumps.

本発明は、半導体素子等の電子部品が実装される配線基板の製造方法において、少なくとも以下の工程を含むことを特徴とする配線基板の製造方法である。
（１）電子部品を実装する際、電子部品の電極又は電極上のバンプが位置する部分の第１の金属板上に、ウエットエチング液に耐性のあるストッパ材を形成する工程。
（２）電極又は電極上にバンプが形成された電子部品を、電極又はバンプが該ストッパ材と重なるように、第１の金属板上に実装する工程。
（３）電子部品が実装された第１の金属板上に、少なくとも絶縁層となる未硬化樹脂設け、熱硬化させる工程。
（４）ウエットエチング液により、第１の金属板を剥離する工程。
（５）絶縁層表面に無電解めっき及び電解めっき法により、導体層を形成する工程。
（６）基板の両面に配線を形成する工程。 The present invention is a method for manufacturing a wiring board on which an electronic component such as a semiconductor element is mounted, and includes at least the following steps.
(1) A step of forming a stopper material resistant to a wet etching solution on the first metal plate in a portion where an electrode of the electronic component or a bump on the electrode is located when mounting the electronic component.
(2) A step of mounting the electrode or the electronic component on which the bump is formed on the first metal plate such that the electrode or the bump overlaps the stopper material.
(3) A step of providing an uncured resin which is at least an insulating layer on the first metal plate on which the electronic component is mounted, and thermally curing it.
(4) A step of peeling the first metal plate with a wet etching solution.
(5) A step of forming a conductor layer on the surface of the insulating layer by electroless plating and electrolytic plating.
(6) A step of forming wiring on both sides of the substrate.

また本発明は、半導体素子等の電子部品が実装される配線基板の製造方法において、上記請求項１の「（５）絶縁層表面に無電解めっき及び電解めっき法により、導体層を形成する工程」の前に、ストッパ材を除去する工程を含むことを特徴とする請求項１記載の配線基板の製造方法である。   Further, the present invention provides a method for manufacturing a wiring board on which an electronic component such as a semiconductor element is mounted, wherein “(5) the step of forming a conductor layer on the surface of the insulating layer by electroless plating and electrolytic plating”. The method of manufacturing a wiring board according to claim 1, further comprising a step of removing the stopper material before ‘.

また本発明は、上記請求項１「（２）電極又は電極上にバンプが形成された電子部品を、電極又はバンプが該ストッパ材と重なるように、第１の金属板上に実装する工程」において、電極又は電極上にバンプが形成された電子部品を、接着剤を介して、バンプが該ストッパ材と重なるように、第１の金属板上に実装することを特徴とする請求項１、２記載の配線基板の製造方法である。   In addition, the present invention provides the above-mentioned claim 1 "(2) a step of mounting the electrode or the electronic component on which the bump is formed on the first metal plate so that the electrode or the bump overlaps the stopper material" The electronic component having a bump formed on the electrode is mounted on the first metal plate via an adhesive so that the bump overlaps the stopper material. 2. A method for producing a wiring board according to 2.

また本発明は、ブラスト法によりストッパ材を除去することを特徴とする請求項１、２及び３記載の配線基板の製造方法である。   The present invention is the method for manufacturing a wiring board according to claim 1, 2 or 3, wherein the stopper material is removed by a blast method.

本発明は、ストッパ材を除去すると同時に、ストッパ材が存在する面とは反対側の面より、少なくとも部品の一部表面を露出させることを特徴とする請求項２記載の配線基板の
製造方法である。 3. The method of manufacturing a wiring board according to claim 2, wherein at least a part of the surface of the component is exposed from the surface opposite to the surface on which the stopper material exists simultaneously with the removal of the stopper material. is there.

本発明の配線基板の製造方法では以上のような構成であるから、半導体素子およびチップ部品は上層との接続構造となる。これによって、上層と最短距離で接続を図ることが可能となり、配線設計の自由度が大きく、配線基板を小さくでき、また、他の部品接続の配線長が短いことから、電気的特性を向上させることが可能となる。   Since the wiring board manufacturing method of the present invention has the above-described configuration, the semiconductor element and the chip component have a connection structure with the upper layer. As a result, it is possible to connect to the upper layer at the shortest distance, the degree of freedom in wiring design is large, the wiring board can be made small, and the wiring length for connecting other components is short, thereby improving the electrical characteristics. It becomes possible.

また、本発明の配線基板の製造方法では、上層配線と直接接続する事より、従来複数の加工条件があったレーザービア加工や、深さの異なるビアめっき制御の必要がなくなり、生産性が向上し、また、バンプ径が小さくなっても、レーザー加工の位置ズレにより起こっていた半導体素子上の配線等を破壊してしまうといった問題がなくなる。   In addition, in the method for manufacturing a wiring board according to the present invention, since it is directly connected to the upper layer wiring, there is no need for laser via processing and conventional via plating control with different depths, and productivity is improved. In addition, even if the bump diameter is reduced, there is no problem that the wiring on the semiconductor element or the like caused by the positional deviation of the laser processing is destroyed.

また、本発明の配線基板の製造方法では、エッチング液による腐食を防止するストッパ材があるため、電極がスズ、ニッケル、銅で形成された一般市販品の安価なチップ部品および、銅バンプ等の安価なバンプ付半導体素子を使用することが可能となり、低コストで内蔵することが可能となる。   Further, in the method for manufacturing a wiring board according to the present invention, since there is a stopper material that prevents corrosion due to the etching solution, an inexpensive chip component of a general commercial product in which the electrode is formed of tin, nickel, copper, and a copper bump, etc. An inexpensive semiconductor device with bumps can be used, and it can be built at a low cost.

更に、本発明の配線基板の製造方法では、金属等のマスクを用いて、ストッパ材が存在する面とは反対側の面より部品の一部を露出させる。部品の露出した面に銅めっきすることで、放熱性を向上させることができる。   Furthermore, in the method for manufacturing a wiring board according to the present invention, a part of the component is exposed from the surface opposite to the surface where the stopper material exists using a mask made of metal or the like. Heat dissipation can be improved by copper plating on the exposed surface of the component.

以下に本発明に係る配線板の製造方法の一実施形態について、図面（図１及び図２）に基づいて詳細に説明する。   Hereinafter, an embodiment of a method for producing a wiring board according to the present invention will be described in detail with reference to the drawings (FIGS. 1 and 2).

図１及び図２は本発明による配線基板の製造方法における一例の説明図である。   1 and 2 are explanatory views of an example in the method for manufacturing a wiring board according to the present invention.

図１（ａ）に示すように、第１の金属板１、例えば、３５μｍ厚の銅箔１０１の粗化面側にストッパ材２を設ける。粗化面側にストッパ材２を設けるのは、銅箔１０１のストッパ材２側になる半導体素子３やチップ部品４の内蔵時の絶縁層５と銅箔１０１の接着力を上げて、工程中に剥離が起こらないためである。また、銅箔エッチング後の絶縁層表面が粗れていることにより、絶縁層上の銅めっきの密着性を確保する目的である。   As shown in FIG. 1A, a stopper material 2 is provided on the roughened surface side of a first metal plate 1, for example, a 35 μm thick copper foil 101. The stopper material 2 is provided on the roughened surface side in order to increase the adhesive force between the insulating layer 5 and the copper foil 101 when the semiconductor element 3 and the chip component 4 on the copper foil 101 side are embedded, This is because peeling does not occur. Moreover, it is the objective of ensuring the adhesiveness of the copper plating on an insulating layer because the insulating layer surface after copper foil etching is rough.

ストッパ材２の形成方法としては、銅箔１０１の両面にフォトレジストを形成し、露光、現像を行い、少なくともストッパ材２となる部分の銅箔１０１表面を露出させた後、金等の、エッチング液に耐腐食性のある金属を電解めっきにて形成した後フォトレジストを剥離する方法や、スクリーン印刷によりエポキシ系樹脂等を印刷する方法が挙げられる。ここで、エッチング液は塩化第２鉄液や塩化第２銅液等である。   As a method of forming the stopper material 2, a photoresist is formed on both surfaces of the copper foil 101, exposure and development are performed, and at least the surface of the copper foil 101 serving as the stopper material 2 is exposed, and then etching such as gold is performed. Examples thereof include a method of peeling a photoresist after forming a metal having corrosion resistance in a liquid by electrolytic plating, and a method of printing an epoxy resin or the like by screen printing. Here, the etching solution is a ferric chloride solution or a cupric chloride solution.

次に、図１（ｂ）に示すように、金バンプ、銅バンプが形成された半導体素子３や、電極がスズ、ニッケル、銅で形成された安価な市販品のチップ部品４等の電子部品をＮＣＦ（Non-conductive Film）等の接着剤を介して、電極やバンプが所望のストッパ材２と接するように、銅箔１０１上に実装する。   Next, as shown in FIG. 1B, an electronic component such as a semiconductor element 3 on which gold bumps or copper bumps are formed, or an inexpensive commercially available chip component 4 in which electrodes are formed of tin, nickel, or copper. Is mounted on the copper foil 101 via an adhesive such as NCF (Non-conductive Film) so that the electrodes and bumps are in contact with the desired stopper material 2.

次に、図１（ｃ）に示すように、電子部品が内蔵される絶縁層５となる未硬化な絶縁樹脂、例えば、エポキシ系樹脂を介し、第２の金属板６、例えば、銅箔１０１との積層を行う。   Next, as shown in FIG. 1C, a second metal plate 6, for example, a copper foil 101 is interposed through an uncured insulating resin, for example, an epoxy resin, which becomes the insulating layer 5 in which the electronic component is incorporated. And laminating.

次に、図１（ｄ）に示すように、エッチング液により、少なくとも第１の金属板１の一
部を除去し、ストッパ材２を露出させる。 Next, as shown in FIG. 1 (d), at least a part of the first metal plate 1 is removed with an etching solution to expose the stopper material 2.

なお、ストッパ材２が非金属の場合は、図２に示すように、必ず、ウエットブラスト等の物理的方法、或いは、電極やバンプが腐食されない薬液でストッパ材２を剥離する。   When the stopper material 2 is non-metallic, as shown in FIG. 2, the stopper material 2 is always peeled off by a physical method such as wet blasting or a chemical solution that does not corrode the electrodes and bumps.

次に、図１（ｅ）に示すように、炭酸ガスレーザーにて、所望のビア穴を開け、無電解銅めっき及び電解銅めっき法により、両面の導通を図るビア１４、及び絶縁層５表面に導体層７を形成する。   Next, as shown in FIG. 1 (e), a via hole is formed with a carbon dioxide laser, and the via 14 and the surface of the insulating layer 5 are made conductive on both sides by electroless copper plating and electrolytic copper plating. A conductor layer 7 is formed on the substrate.

次いで、図１（ｆ）に示すように、フォトレジストを形成し、露光、現像を行い、配線８として残す部分以外の導体層７表面を露出させ、次に塩化第２鉄液等にて露出した銅を除去し、フォトレジストを剥離することで上層配線８層を形成する。   Next, as shown in FIG. 1 (f), a photoresist is formed, exposed and developed to expose the surface of the conductor layer 7 except for the portion left as the wiring 8, and then exposed with ferric chloride solution or the like. The copper thus removed is removed, and the upper layer wiring 8 layers are formed by removing the photoresist.

次いで、絶縁層及び導体層を積層し多層化することで、電子部品を内蔵した配線基板を作製する。   Next, an insulating layer and a conductor layer are stacked to form a multilayer, thereby producing a wiring board with a built-in electronic component.

以下に、本発明に係る具体的実施例について説明する。    Specific examples according to the present invention will be described below.

＜実施例１＞
図３に従って、実施例１を説明する。まず、１８μｍ厚の銅箔１０１の平滑面側に、粘着材（強度０.６Ｎ／ｃｍ）が形成された工程耐性のある５０μｍ厚のペンフィルム（ポリエチレンナフタレートフィルム）９を、銅箔１０１の粗化面には解像度２０μｍ、厚さ１５μｍのめっき液耐性のあるドライフィルムフォトレジストを形成し、所望の露光現像を行い、ストッパ材を形成する銅箔１０１表面を露出させた。ここで、ペンフィルム９は、工程を流す際の補強材となるものであり、本発明において必ず必要なものではない。 <Example 1>
Example 1 will be described with reference to FIG. First, a 50 μm-thick pen film (polyethylene naphthalate film) 9 having a process resistance, in which an adhesive (strength 0.6 N / cm) is formed on the smooth surface side of the 18 μm-thick copper foil 101, On the roughened surface, a dry film photoresist having a plating solution resistance of 20 μm in resolution and 15 μm in thickness was formed and subjected to desired exposure and development to expose the surface of the copper foil 101 forming the stopper material. Here, the pen film 9 serves as a reinforcing material when the process flows, and is not necessarily required in the present invention.

次いで、図３（ａ）に示すように、電解めっきにより、ニッケルを１μｍ、金を０.０１μｍ程度設けてストッパ材を形成し、ドライフィルムフォトレジストを剥離した。   Next, as shown in FIG. 3A, a stopper material was formed by electrolytic plating to provide nickel of about 1 μm and gold of about 0.01 μm, and the dry film photoresist was peeled off.

次に、ボールボンディング装置で形成された高さ４０μｍの金バンプを有する厚さ１５０μｍの半導体素子３および、電極がスズ、ニッケル、銅で形成された低背位０６０３、高さ１５０μｍのキャパシタのチップ部品４の電子部品をＮＣＦ（Non-conductive Film）の接着剤１０を介して、バンプや電極が所望のストッパ材２である金と接するように、銅箔１０１上に実装し、図３（ｂ）に示すように、実装基材１１を作製した。   Next, a semiconductor chip 3 having a thickness of 150 μm having a gold bump having a height of 40 μm formed by a ball bonding apparatus, and a low profile 0603 in which electrodes are formed of tin, nickel and copper, and a capacitor chip having a height of 150 μm. The electronic component 4 is mounted on the copper foil 101 via an NCF (Non-conductive Film) adhesive 10 so that the bumps and electrodes are in contact with the gold as the desired stopper material 2. The mounting substrate 11 was produced as shown in FIG.

次いで、図３（ｃ）及び（ｄ）に示すように、実装基材１１と、電子部品に位置する所望の窓が開いた１００μｍ厚ガラスクロス入りプリプレグ材１２と、電子部品に位置する所望の窓が開いた１００μｍ厚の両面配線基板１３と、１００μｍ厚ガラスクロス入りプリプレグ材１２と、１８μｍ厚の銅箔１０１の構成でピンラミネーション積層を行った。   Next, as shown in FIGS. 3C and 3D, the mounting substrate 11, the prepreg material 12 with a 100 μm-thick glass cloth having a desired window located in the electronic component opened, and the desired component located in the electronic component. Pin lamination was performed using a 100 μm-thick double-sided wiring board 13 with a window open, a 100 μm-thick glass cloth-containing prepreg material 12, and a 18 μm-thick copper foil 101.

次に、図３（ｅ）に示すように、ペンフィルム９を剥がし、更に図３（ｆ）に示すように、両面の銅箔１０１及びストッパ材２部のニッケルを塩化第２鉄液を用いてエッチングにより、除去した。   Next, as shown in FIG. 3 (e), the pen film 9 is peeled off. Further, as shown in FIG. 3 (f), the copper foil 101 on both sides and the nickel of the stopper material 2 parts are used with ferric chloride solution. Then, it was removed by etching.

次いで、炭酸ガスレーザーにて、所望のビア穴を開け、無電解銅めっきおよび電解銅めっきを行い、図３（ｇ）に示すように、両面配線基板１３との導通を図るビア１４、及び導体層７を形成した。   Next, a desired via hole is made with a carbon dioxide laser, electroless copper plating and electrolytic copper plating are performed, and as shown in FIG. Layer 7 was formed.

次いで、ドライフィルムフォトレジストを形成し、所望の露光現像を行い、配線８とし
て残す部分以外の導体層７表面を露出させ、次に塩化第２鉄液にて露出した導体層７を除去し、ドライフィルムフォトレジストを剥離することで、図３（ｈ）に示すように、上層配線８層を形成した。
次いで、絶縁層５及び導体層７を積層し多層化する積層工程等の残された一連の配線基板の製造工程を行う事で、本発明に係る電子部品を内蔵した配線基板を作製した。 Next, a dry film photoresist is formed, the desired exposure and development is performed, the surface of the conductor layer 7 other than the portion left as the wiring 8 is exposed, and then the conductor layer 7 exposed with the ferric chloride solution is removed, By peeling off the dry film photoresist, as shown in FIG. 3H, 8 upper wiring layers were formed.
Next, a series of manufacturing steps of the remaining wiring substrate such as a stacking step of stacking the insulating layer 5 and the conductor layer 7 to form a multilayer was performed, thereby manufacturing a wiring substrate incorporating the electronic component according to the present invention.

＜実施例２＞
まず、実施例１と同様にして、１８μｍ厚の銅箔１０１の平滑面側に、粘着材（強度０.６Ｎ／ｃｍ程度）が形成された工程耐性のある５０μｍ厚のペンフィルム（ポリエチレンナフタレートフィルム）９を、銅箔１０１の粗化面には解像度２０μｍ、厚さ１５μｍのめっき液耐性のあるドライフィルムフォトレジストを形成し、所望の露光現像を行い、ストッパ材２を形成する銅箔１０１表面を露出させた。 <Example 2>
First, in the same manner as in Example 1, a 50 μm-thick pen film (polyethylene naphthalate) having a process resistance in which an adhesive (strength of about 0.6 N / cm) is formed on the smooth surface side of an 18 μm-thick copper foil 101. Film) 9 is formed on the roughened surface of the copper foil 101 by forming a plating film resistant dry film photoresist having a resolution of 20 μm and a thickness of 15 μm, and performing desired exposure and development to form the stopper material 2. The surface was exposed.

次いで、電解めっきにより、ニッケルを１μｍ、金を０.０１μｍ程度設け、ドライフィルムフォトレジストを剥離した。   Then, by electrolytic plating, nickel of about 1 μm and gold of about 0.01 μm were provided, and the dry film photoresist was peeled off.

次に、ボールボンディング装置で形成された高さ４０μｍの金バンプを有する厚さ１５０μｍの半導体素子３および、電極がスズ、ニッケル、銅で形成された低背位０６０３、高さ１５０μｍのキャパシタのチップ部品４の電子部品をＮＣＦ（Non-conductive Film）の接着剤１０を介して、バンプや電極が所望のストッパ材２である金と接するように、銅箔１０１上に実装し、実装基材１１を作製した。   Next, a semiconductor chip 3 having a thickness of 150 μm having a gold bump having a height of 40 μm formed by a ball bonding apparatus, and a low profile 0603 in which electrodes are formed of tin, nickel and copper, and a capacitor chip having a height of 150 μm. The electronic component 4 is mounted on the copper foil 101 via an NCF (Non-conductive Film) adhesive 10 so that the bumps and electrodes are in contact with gold as the desired stopper material 2, and the mounting substrate 11 is mounted. Was made.

次いで、実装基材１１と、電子部品に位置する所望の窓が開いた１００μｍ厚ガラスクロス入りプリプレグ材１２と、電子部品に位置する所望の窓が開いた１００μｍ厚の両面配線基板１３と、１００μｍ厚ガラスクロス入りプリプレグ材１２と、１８μｍ厚の銅箔１０１の構成でピンラミネーション積層を行った。   Next, the mounting substrate 11, the prepreg material 12 with a 100 μm-thick glass cloth in which a desired window located on the electronic component is opened, the 100 μm-thick double-sided wiring board 13 in which the desired window located on the electronic component is opened, and 100 μm Pin lamination was performed using a prepreg material 12 containing a thick glass cloth and a copper foil 101 having a thickness of 18 μm.

次に、ペンフィルム９を剥がし、両面の銅箔１０１及びストッパ材２部のニッケルを塩化第２鉄液により、除去した。ここまでの工程は、実施例１と同様である。   Next, the pen film 9 was peeled off, and the copper foil 101 on both sides and the nickel in 2 parts of the stopper material were removed with a ferric chloride solution. The steps up to here are the same as in the first embodiment.

ここで、約６μｍ径のアルミナの微細砥粒をエアー圧０.２ＭＰａで、幅広ノズルから噴出させ、対象物の表面を削るウエットブラスト法により物理的にストッパ材２を除去することで、図４に示すように、半導体素子３上の金バンプ及びキャパシタのチップ部品４上のスズ電極を露出させた。これによって、電子部品と上層配線の接続はめっき接続となる。なおこの際、絶縁層も１μｍ程度削れた。   Here, the fine abrasive grains of alumina having a diameter of about 6 μm are ejected from a wide nozzle at an air pressure of 0.2 MPa, and the stopper material 2 is physically removed by a wet blasting method in which the surface of the object is shaved. As shown, the gold bumps on the semiconductor element 3 and the tin electrode on the capacitor chip component 4 were exposed. Thus, the connection between the electronic component and the upper layer wiring is a plating connection. At this time, the insulating layer was also cut by about 1 μm.

次いで実施例１と同様に、炭酸ガスレーザーにて、所望のビア穴を開け、無電解銅めっきおよび電解銅めっきを行い、両面配線基板１３との導通を図るビア１４、及び導体層７を形成した。次いで、ドライフィルムフォトレジストを形成し、所望の露光現像を行い、配線８となる導体層７以外の導体層７表面を露出させた。次に、塩化第２鉄液等にて露出した導体層７を除去し、ドライフィルムフォトレジストを剥離することで上層配線８層を形成した。   Next, in the same manner as in Example 1, a desired via hole is made with a carbon dioxide laser, electroless copper plating and electrolytic copper plating are performed, and a via 14 and a conductor layer 7 are formed to establish conduction with the double-sided wiring board 13. did. Next, a dry film photoresist was formed, and a desired exposure and development was performed to expose the surface of the conductor layer 7 other than the conductor layer 7 to be the wiring 8. Next, the conductor layer 7 exposed with a ferric chloride solution or the like was removed, and the dry film photoresist was peeled to form eight upper wiring layers.

次いで、絶縁層５及び導体層７を積層し多層化する積層工程等の残された一連の配線基板の製造工程を行う事で、本発明に係る電子部品を内蔵した配線基板を作製した。   Next, a series of manufacturing steps of the remaining wiring substrate such as a stacking step of stacking the insulating layer 5 and the conductor layer 7 to form a multilayer was performed, thereby manufacturing a wiring substrate incorporating the electronic component according to the present invention.

本発明の配線基板の製造方法は、特に、携帯機器等の配線基板を小型化させ、電気的特性を向上させるといった、能動素子や受動素子を内蔵する配線基板の製造に利用でき、低コストの内蔵配線基板の製造方法を提供することができる。   The method for manufacturing a wiring board according to the present invention can be used for manufacturing a wiring board that incorporates active elements and passive elements, such as miniaturizing wiring boards for portable devices and the like, and improving electrical characteristics. A method for manufacturing a built-in wiring board can be provided.

本発明の配線基板の製造方法の一例を断面で示す説明図である。It is explanatory drawing which shows an example of the manufacturing method of the wiring board of this invention in a cross section. 本発明の配線基板の製造方法の一例において、ストッパ材を除去した後の様子を断面で示す説明図である。It is explanatory drawing which shows a mode after removing a stopper material in an example of the manufacturing method of the wiring board of this invention in a cross section. 本発明の配線基板の製造方法の実施例を断面で示す説明図である。It is explanatory drawing which shows the Example of the manufacturing method of the wiring board of this invention in a cross section. 本発明の配線基板の製造方法の実施例において、ストッパ材を除去した後の様子をで示す説明図である。In the Example of the manufacturing method of the wiring board of this invention, it is explanatory drawing which shows a mode after removing a stopper material. 従来の配線基板の製造方法の第１の例を断面で示す説明図である。It is explanatory drawing which shows the 1st example of the manufacturing method of the conventional wiring board in a cross section. 従来の配線基板の製造方法の第2の例を断面で示す説明図である。FIG. 10 is an explanatory view showing, in section, a second example of a conventional method for manufacturing a wiring board. 従来の配線基板の製造方法の第3の例を断面で示す説明図である。FIG. 10 is an explanatory view showing a third example of a conventional method of manufacturing a wiring board in cross section.

符号の説明Explanation of symbols

１・・・第１の金属板
１０１・・・銅箔
２・・・ストッパ材
３・・・半導体素子
４・・・チップ部品
５・・・絶縁層
６・・・第２の金属板
７・・・導体層
８・・・配線
９・・・ペンフィルム
１０・・・接着剤
１１・・・実装基板
１２・・・プリプレグ材
１３・・・両面配線基板
１４・・・ビア
１５・・・途中工程である基板
１６・・・ビア穴 DESCRIPTION OF SYMBOLS 1 ... 1st metal plate 101 ... Copper foil 2 ... Stopper material 3 ... Semiconductor element 4 ... Chip component 5 ... Insulating layer 6 ... 2nd metal plate 7 .... Conductor layer 8 ... Wiring 9 ... Pen film 10 ... Adhesive 11 ... Mounting substrate 12 ... Pre-preg material 13 ... Double-sided wiring board 14 ... Via 15 ... On the way Process substrate 16 ... via hole

Claims (5)

電子部品が実装される配線基板の製造方法において、少なくとも以下の工程を含むことを特徴とする配線基板の製造方法。
（１）電子部品を実装する際、電子部品の電極又は電極上のバンプが位置する部分の第１
の金属板上に、ウエットエチング液に耐性のあるストッパ材を形成する工程。
（２）電極又は電極上にバンプが形成された電子部品を、電極又はバンプが該ストッパ材
と重なるように、第１の金属板上に実装する工程。
（３）電子部品が実装された第１の金属板上に、少なくとも絶縁層となる未硬化樹脂層を
設け、熱硬化させる工程。
（４）ウエットエチング液により、第１の金属板を剥離する工程。
（５）絶縁層表面に無電解めっき及び電解めっき法により、導体層を形成する工程。
（６）基板の両面に配線を形成する工程。 A method for manufacturing a wiring board on which an electronic component is mounted, comprising at least the following steps.
(1) When the electronic component is mounted, the first of the portion where the electrode of the electronic component or the bump on the electrode is located
Forming a stopper material resistant to the wet etching solution on the metal plate.
(2) A step of mounting the electrode or the electronic component on which the bump is formed on the first metal plate such that the electrode or the bump overlaps the stopper material.
(3) A step of providing at least an uncured resin layer serving as an insulating layer on the first metal plate on which the electronic component is mounted and thermally curing it.
(4) A step of peeling the first metal plate with a wet etching solution.
(5) A step of forming a conductor layer on the surface of the insulating layer by electroless plating and electrolytic plating.
(6) A step of forming wiring on both sides of the substrate. （５）の工程の前に、ストッパ材を除去する工程を含むことを特徴とする請求項１記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 1, further comprising a step of removing the stopper material before the step (5). （２）の工程において、電極又は電極上にバンプが形成された電子部品を、接着剤を介して、バンプが該ストッパ材と重なるように、第１の金属板上に実装することを特徴とする請求項１、２記載の配線基板の製造方法。   In the step (2), the electronic component having the bump formed on the electrode or the electrode is mounted on the first metal plate through an adhesive so that the bump overlaps the stopper material. The method for manufacturing a wiring board according to claim 1 or 2. ブラスト法によりストッパ材を除去することを特徴とする請求項２及び３記載の配線基板の製造方法。   4. The method for manufacturing a wiring board according to claim 2, wherein the stopper material is removed by a blast method. ストッパ材を除去すると同時に、ストッパ材が存在する面とは反対側の面より、少なくとも電子部品の一部表面を露出させることを特徴とする請求項２〜４いずれか1項記載の配線基板の製造方法。   5. The wiring board according to claim 2, wherein at least a part of the surface of the electronic component is exposed from the surface opposite to the surface on which the stopper material exists simultaneously with the removal of the stopper material. Production method.
JP2007125400A 2007-05-10 2007-05-10 Wiring board manufacturing method Pending JP2008282953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007125400A JP2008282953A (en) 2007-05-10 2007-05-10 Wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007125400A JP2008282953A (en) 2007-05-10 2007-05-10 Wiring board manufacturing method

Publications (1)

Publication Number Publication Date
JP2008282953A true JP2008282953A (en) 2008-11-20

Family

ID=40143533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007125400A Pending JP2008282953A (en) 2007-05-10 2007-05-10 Wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JP2008282953A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013093614A (en) * 2010-05-25 2013-05-16 Samsung Electro-Mechanics Co Ltd Embedded printed circuit board and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013093614A (en) * 2010-05-25 2013-05-16 Samsung Electro-Mechanics Co Ltd Embedded printed circuit board and method of manufacturing the same

Similar Documents

Publication Publication Date Title
US10034368B2 (en) Flying tail type rigid-flexible printed circuit board
US8238114B2 (en) Printed wiring board and method for manufacturing same
JP4876272B2 (en) Printed circuit board and manufacturing method thereof
CN105228341B (en) Printed circuit board, package substrate and its manufacturing method
US8941016B2 (en) Laminated wiring board and manufacturing method for same
JP6711509B2 (en) Printed circuit board, semiconductor package and manufacturing method thereof
JP4555852B2 (en) Circuit board manufacturing method
US9713267B2 (en) Method for manufacturing printed wiring board with conductive post and printed wiring board with conductive post
JP2007165888A (en) Printed-circuit substrate in which electron devices are built, and its manufacturing method
CN100551206C (en) Make the method for rigid-flexible printed circuit board
KR102333091B1 (en) Printed circuit board and method of manufacturing the same
US9554462B2 (en) Printed wiring board
US20140116759A1 (en) Printed wiring board and method for manufacturing printed wiring board
JPWO2009118925A1 (en) Electronic component built-in wiring board and manufacturing method thereof
JP2009158912A (en) Package substrate and method of manufacturing the same
CN104247582A (en) Printed circuit board and method of manufacturing the same
KR20110064216A (en) Circuit board with bumps and manufacturing method thereof
JP2008182071A (en) Electronic component built-in wiring board, method for manufacturing the same, and electronic device
JP4863076B2 (en) Wiring board and manufacturing method thereof
JP2014204088A (en) Multilayer wiring board and method of manufacturing the same
JP2008282953A (en) Wiring board manufacturing method
JP5836019B2 (en) Component built-in substrate and manufacturing method thereof
JP5098313B2 (en) Wiring board
JP4347143B2 (en) Circuit board and manufacturing method thereof
KR100796981B1 (en) Printed Circuit Board Manufacturing Method