JPS6417136A - Invalidation control system for cache memory - Google Patents

Abstract

PURPOSE:To carry out the access to a 1st bus and the invallidation of a cache memory in parallel with each other by delivering the using request address of the 1st bus given from a processing control part which performs the processing within a data processing means to the 1st bus after latching said request address. CONSTITUTION:Each of plural data processing means 113 gives an access to a 1st bus 111 and processes data. Each means 113 gives an access to a 2nd bus 115 connected in response to the bus 111 for access to the data on a memory 117. Furthermore each means 113 contains a cache memory 119 that can store data as necessary and at the same time requires the invalidation of those stored data. The using request address of the bus 111 received from a processing control part 121 is latched by each means 113 and outputted to the bus 111. Thus the data on the memory 119 are invalidated in accordance with said request address. As a result, the memory 119 can be invalidated concurrently with the access to the bus 111.