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JPS6459537A - System for controlling cache memory of data processor - Google Patents

System for controlling cache memory of data processor

Info

Publication number
JPS6459537A
JPS6459537A JP62217631A JP21763187A JPS6459537A JP S6459537 A JPS6459537 A JP S6459537A JP 62217631 A JP62217631 A JP 62217631A JP 21763187 A JP21763187 A JP 21763187A JP S6459537 A JPS6459537 A JP S6459537A
Authority
JP
Japan
Prior art keywords
cache memory
output
data processor
pipeline
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62217631A
Other languages
Japanese (ja)
Inventor
Hideki Osone
Atsushi Ike
Masahito Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62217631A priority Critical patent/JPS6459537A/en
Publication of JPS6459537A publication Critical patent/JPS6459537A/en
Pending legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To speed up a processing, by enabling data in the cache memory on one side of a pipeline to be made access from another pipeline when a vacant pipeline exists. CONSTITUTION:Selectors 52 and 53 are provided between an address generating phase and an address conversion phase, respectively, and they receive the output of two address generating phases 3 and 6, and select and output either of them. Selectors 54 and 55 are provided between a cache readout phase and a register, respectively, and they receive the output of two cache readout phases 5 an 8, and select and memorize either of them. In such a way, it is possible to utilize data in the cache memory of a processing system on one side by another processing system, thereby, the processing speed can be accelerated.
JP62217631A 1987-08-31 1987-08-31 System for controlling cache memory of data processor Pending JPS6459537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62217631A JPS6459537A (en) 1987-08-31 1987-08-31 System for controlling cache memory of data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62217631A JPS6459537A (en) 1987-08-31 1987-08-31 System for controlling cache memory of data processor

Publications (1)

Publication Number Publication Date
JPS6459537A true JPS6459537A (en) 1989-03-07

Family

ID=16707298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62217631A Pending JPS6459537A (en) 1987-08-31 1987-08-31 System for controlling cache memory of data processor

Country Status (1)

Country Link
JP (1) JPS6459537A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03235145A (en) * 1990-02-13 1991-10-21 Agency Of Ind Science & Technol Cache memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03235145A (en) * 1990-02-13 1991-10-21 Agency Of Ind Science & Technol Cache memory device

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