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JPS6418858A - Storing control system - Google Patents

Storing control system

Info

Publication number
JPS6418858A
JPS6418858A JP62175565A JP17556587A JPS6418858A JP S6418858 A JPS6418858 A JP S6418858A JP 62175565 A JP62175565 A JP 62175565A JP 17556587 A JP17556587 A JP 17556587A JP S6418858 A JPS6418858 A JP S6418858A
Authority
JP
Japan
Prior art keywords
cpu
data
mcu
storing
bytes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62175565A
Other languages
Japanese (ja)
Inventor
Yukihiko Kitano
Kazuhiro Hara
Takeshi Suzuki
Tsuyoshi Honkurumada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62175565A priority Critical patent/JPS6418858A/en
Publication of JPS6418858A publication Critical patent/JPS6418858A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To increase a processing speed with a storing control system by extending the storing data given from a CPU up to the 1-block width of a buffer storage in the CPU and storing said data in the continuous addresses of a main memory. CONSTITUTION:In case the same data are continuously stored over plural bytes, only the storing data equivalent to 8 bytes of the storing data bus width, for example, is transferred to a memory control unit (MCU) 2 from a CPU 1. Then the storing data is extended within the MCU 2 up to the 1-block width (e.g., 32 bytes) of a buffer storage in the CPU 1 and stored in a main memory 3. Thus the data transfer frequency is decreased between the CPU 1 and the MCU 2 and at the same time the data are stored continuously into the memory 3 within the MCU 2.
JP62175565A 1987-07-14 1987-07-14 Storing control system Pending JPS6418858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62175565A JPS6418858A (en) 1987-07-14 1987-07-14 Storing control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62175565A JPS6418858A (en) 1987-07-14 1987-07-14 Storing control system

Publications (1)

Publication Number Publication Date
JPS6418858A true JPS6418858A (en) 1989-01-23

Family

ID=15998303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62175565A Pending JPS6418858A (en) 1987-07-14 1987-07-14 Storing control system

Country Status (1)

Country Link
JP (1) JPS6418858A (en)

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