JPS63211642A - Apparatus for testing semiconductor - Google Patents

Abstract

PURPOSE:To prevent positional displacement to a wafer of a probing card by forming a second defective-mark giving member through-hole to a socket for fitting a sample IC mounted made to correspond to a probe in a positional manner while being made to correspond to a first defective-mark giving member through-hole for the probing card in the positional manner. CONSTITUTION:When a defective mark must be given to an integrated circuit element on a wafer 9 during a wafer test, a defective-mark giving member is passed through a defective-mark giving member through-hole 10 for a socket 7 for fitting a sample IC and a defective-mark giving member through-hole 2 for a probing card 1 in succession. According to such a wafer test, only the sample IC 8 may be set up to the socket 7 for fitting the sample IC even when wafer test debug must be conducted during the test, and force working to the probing card 1 on the mounting work is reduced, thus generating no positional displacement to the wafer 9 of the probing card 1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor testing device, and in particular, a probe for wafer testing is arranged on one side of a probe card, and the above-mentioned probe is arranged on the other side of the probe card. The present invention relates to an improvement in a semiconductor testing device in which sockets for mounting sample ICs for wafer test and debugging are provided in corresponding positions.

[Conventional technology]

Usually, integrated circuit elements formed on a wafer are tested (hereinafter referred to as a "wafer test") using a semiconductor testing device before being separated into chips for each integrated circuit element. FIG. 4 is a side view of a conventional semiconductor testing apparatus used for such wafer testing, and FIG. 5 is a plan view thereof.

As shown in both figures, a ring-shaped fixing frame 3 is attached to the lower side of the probe card 1 around the periphery of the defective marking member insertion hole 2 provided at the center, and the lower side of the fixing frame 3 is A plurality of inspection probes 4 for wafer testing are arranged to protrude downward. Each of these probes 4 is electrically connected to a plurality of lead wires 5 provided on the upper surface side of the probe card 1 via a fixed frame 3.
is configured to be electrically connected to a tester (not shown) via a cable (not shown).

On the other hand, a ring-shaped socket pedestal 6 is attached to the top side of the probe card 1 in a position corresponding to the fixed frame 3.
A sample IC mounting socket 7 for wafer test and debugging is freely mounted on this socket pedestal 6. As shown in the plan view in FIG. 6, the sample IC mounting socket 7 includes a socket main body 7a having a plurality of terminal quantities 7C, and a plurality of terminal quantities 7C connected to a plurality of terminals of a socket pedestal 6 (not shown). and a connector 7b for electrical connection to each of the sample ICs 8 and 7b, and when a plurality of terminals (not shown) of the sample IC 8 are connected to the terminals 7C of the socket main body 7a as shown by imaginary lines in FIG.
A plurality of terminals are electrically connected to a plurality of lead wires 5 provided on the upper surface side of the probe card 1 via a sample IC mounting socket 7 and a socket pedestal 6, respectively. The reason why the sample IC mounting socket 7 is provided in positional correspondence with the probe 4 is to enable accurate wafer test debugging, which will be described later. That is, if the sample IC mounting socket 7 is provided at a position that does not correspond to the probe 4, for example, at the top corner of the probe card 1, in order to electrically connect the sample IC mounting socket 7 to the lead wire 5, the probe card 1 A new lead wire is required from the corner to the center of the wafer, and stray capacitance accumulates in the lead wire, reducing the accuracy of wafer test and debugging.

A wafer test using this semiconductor testing device is performed as follows. First, before performing the actual wafer test, wafer test debugging is performed. This wafer test debugging is carried out on sample ICs that have been evaluated as good by the designer.
A test similar to the wafer test was performed using probe card 1. This is to check whether the test program etc. is working properly. The procedure is to attach the sample IC8 to the sample IC mounting socket 7, connect the socket 7 to the socket pedestal 6, connect the cable of the rough tester (not shown) to the lead wire 5, and connect the sample IC8. Connect electrically to the tester. In this state, the tester sends a signal to the sample IC8 in the same manner as in the wafer test, while the sample IC
A signal outputted from the probe card 1 or a test program is taken into a tester to determine whether there is any defect in the probe card 1 or the test program. If there are no abnormalities in these, the process moves on to the actual wafer test.

In the wafer test, first the sample IC 8 is removed from the socket pedestal 6 together with the socket. This is to enable a defective mark applying member (not shown) to be inserted into the defective mark applying member insertion hole 2 of the probe card 1 from above. Next, the tester is activated to move the wafer stage (not shown) on which the wafer 9 (shown by the imaginary line in FIG. have one-on-one contact with Then, according to the test program in the tester (not shown), signals are sent from the tester to the integrated circuit elements on the wafer 9, and at the same time, signals output from the integrated circuit elements are taken into the tester to determine the quality of the integrated circuit elements. do.

At this time, if the integrated circuit element is determined to be defective, a defective marking member (not shown) is applied to the probe card 1 from above.
The defective mark applying member is passed through the insertion hole 2, and a defective mark is applied to the fI4 circuit element.

In this way, when an integrated circuit element is marked as defective or is determined to be good, the wafer stage is moved and a similar test is performed on the next integrated circuit element.

[Problem that the invention seeks to solve]

Incidentally, wafer test debugging is normally performed before wafer testing, but wafer test debugging may be necessary even during wafer testing to confirm whether the semiconductor testing equipment etc. are normal. In this case, it is necessary to reconnect the socket 7 to which the sample IC 8 is attached to the socket pedestal 6. During this connection work, a considerable force is applied to the probe card 1, and the probe card 1 is displaced relative to the wafer 9. Therefore, when restarting the wafer test, the probe card 1 and the wafer 9
There was a problem in that it was necessary to align the position again.

This invention was made in order to solve the above-mentioned problems, and in order to eliminate the influence of stray capacitance in wafer test debugging, the sample IC mounting socket is arranged on the probe card in a positional correspondence with the probe. An object of the present invention is to provide a semiconductor testing device in which a probe card does not shift relative to a wafer even when wafer test debugging is performed during a wafer test.

[Means for solving problems]

In order to achieve the above object, the semiconductor testing device of the present invention provides a semiconductor testing device in which a wafer is placed on one side of a probe card in which a first defective mark applying member insertion hole is provided so as to surround the first defective mark applying member insertion hole. A plurality of probes for testing are arranged, and a sample IC mounting socket for wafer test debugging is mounted on the other side of the probe card in positional correspondence with the probes, and in this sample IC mounting socket, A second defective mark applying member insertion hole is provided in positional correspondence with the first defective mark applying member insertion hole.

[Effect]

In the semiconductor testing device according to the present invention, since the sample IC mounting socket provided in positional correspondence with the probe is provided with a defective mark applying member insertion hole, it is not necessary to apply a defective mark to the integrated circuit element during wafer testing. If this occurs, the defective mark applying member can be passed through the defective mark applying member insertion hole without removing the sample IC mounting socket.

[Embodiments of the invention]

FIG. 1 is a side view of a semiconductor testing device that is an embodiment of the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is a plan view of a sample IC mounting socket employed in this embodiment. As shown in these figures, this semiconductor test equipment is shown in FIG.
The difference from the conventional semiconductor testing device shown in FIG. The only difference is that a defective marking member insertion hole 10 is formed. Since the other configurations are almost the same as those of the conventional example, the same or corresponding parts are given the same reference numerals and the explanation thereof will be omitted.

According to this semiconductor testing device, a wafer test can be performed without removing the sample IC mounting socket 7, as long as the sample IC 8 (shown by the imaginary line in FIG. 1) is removed. That is, when it becomes necessary to apply a defective mark to an integrated circuit element on the wafer 9 during a wafer test, a defective mark applying member (not shown) is inserted into the defective mark applying member insertion hole 10 of the sample IC mounting socket 7. and the defective marking member insertion hole 2 of the probe card 1 in sequence. In this way, when performing a wafer test,
Even when it becomes necessary to perform wafer test debugging during a test, it is sufficient to simply attach the sample IC 8 to the sample IC attachment socket 7, and only a small amount of force is applied to the probe card 1 during this attachment process.
The probe card 1 will not be misaligned with respect to the wafer 9. Therefore, when restarting the wafer test after wafer test debugging is completed, there is no need to newly align the probe card 1 with respect to the wafer 9. Of course, since the sample IC mounting socket 7 is provided in positional correspondence with the probe 4, wafer test debugging can be performed with high accuracy without being affected by stray capacitance.

〔Effect of the invention〕

As explained above, according to the semiconductor testing device of the present invention, the sample IC mounting socket provided in positional correspondence with the probe is positioned in the sample IC mounting socket provided in positional correspondence with the probe card's first defect marking member insertion hole. A corresponding second defect marking member insertion hole is provided, allowing accurate wafer test debugging without the influence of stray capacitance.
Even when wafer test debugging is performed during a wafer test, it is possible to prevent the probe card from being misaligned with respect to the wafer.

[Brief explanation of the drawing]

FIG. 1 is a side view showing a semiconductor testing device which is an embodiment of the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is a plan view of a sample IC mounting socket adopted in this embodiment. FIG. 4 is a side view of a conventional semiconductor testing device, FIG. 5 is a plan view thereof, and FIG. 6 is a plan view of a conventional sample IC mounting socket. In the figure, 1 is a probe card, 2 is a defective mark applying member insertion hole, 4 is a probe, 7 is a sample IC mounting socket, 8 is a sample IC 19 is a wafer, and 10 is a defective mark applying member insertion hole. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A plurality of probes for wafer testing are disposed on one side of the probe card in which the first defective mark applying member insertion hole is provided so as to surround the first defective mark applying member insertion hole, and In a semiconductor testing device in which a socket for mounting a sample IC for wafer test debugging is provided on the other side of the probe card in positional correspondence with the probe, the first defective mark is applied to the socket for mounting the sample IC. A semiconductor testing device characterized in that a second defect marking member insertion hole is provided in positional correspondence with the member insertion hole.