JPS6234353Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt signal width control circuit added to a microcomputer in which interrupt recognition is performed at a level.

In a microcomputer in which interrupts are performed at the signal level, the external interrupt signal is directly supplied to the microcomputer's interrupt terminal, so if the external interrupt signal width is long, the same processing routine may be repeatedly executed many times. FIG. 1 is an example of this, in which the L level of the external interrupt signal S _IN is recognized as an interrupt. Even if the interrupt signal S _IN requests the execution of one interrupt processing routine, if the signal width at L level is long, the interrupt signal terminal will still be at L level even after one interrupt processing is completed, so the interrupt will be generated again. The same interrupt processing routine is executed after recognizing that the interrupt has occurred, and even after that, the interrupt signal is still at the L level, so the same processing routine is executed again, and the execution of the same processing routine is repeated in vain. Such an operation not only lengthens the processing time, but also may pose a practical problem if, for example, the processing routine involves controlling a motor.

The present invention enables execution of a processing routine for an external interrupt signal by adding a simple circuit.
This is a microcomputer MPU that has an external program memory CS and has an interrupt terminal and a terminal that outputs the address ADD for accessing the program memory. a decoder DEC which is connected to a terminal that outputs an output when a specific address for reading a program for interrupt processing is output; and an external interrupt signal S _IN whose output terminal is connected to the interrupt terminal and which causes an interrupt at the signal level. and a flip-flop FF which is set by the output of the decoder and cleared by the output of the decoder. This will be explained in detail below with reference to the illustrated embodiments.

Figure 2 is a block diagram showing an embodiment of the present invention, where MPU is a microcomputer (processor), CS is an external program memory, and DEC is an MPU.
a decoder that receives an address ADD to be output from CS and produces an output when it is a specific address;
FF is a D type (or S-R type) flip-flop. this microcomputer
MPU specifies various addresses ADD of memory CS and reads data (program) from there.
Processing is performed according to DATA, but in response to external interrupt signal S _IN , a specific address of memory CS storing the interrupt processing program is output. As shown in Figure 3, when the leading edge of the signal S _IN falls, the flip-flop FF is set and its output falls to the L level, and the MPU's interrupt terminal receives the L level, so the MPU recognizes the external interrupt. and starts interrupt processing. To start this process, the specific address is first sent and the interrupt processing program is read from the CS. At this time, the specific address is decoded by the decoder DEC to generate a decoder output, and this output is sent to the flip-flop FF. Clear terminal CR is temporarily set to L.
level. This allows flip-flop FF
is cleared and the interrupt terminal becomes H level. At this point, the external interrupt signal S _IN is still at the L level, but since the flip-flop FF is driven only at the falling edge of S _IN , it does not go to the L level again. The fact that the microcomputer has sent the address for accessing the interrupt processing routine means that it has accepted the interrupt, and at this point the signal on the interrupt terminal is returned to H level, so the width of the interrupt signal input to the microcomputer is is reduced to the bare minimum,
Repeating the same processing routine after one interrupt processing is completed is reliably prevented.

As described above, the present invention includes a flip-flop that is set upon the arrival of an external interrupt signal, uses its output to make the microcomputer recognize the interrupt, and is reset when the address is decoded and output when the interrupt is processed. ,
By adding a simple circuit configuration, it is possible to ensure that the interrupt processing routine is executed only once for each interrupt signal reception. Furthermore, since the added circuit is external, there is an advantage that the microcomputer itself does not require any modification. Furthermore, some level interrupt types actively utilize repeated execution of interrupt processing routines to adjust the time, but in such cases, the additional circuitry is bypassed and the external interrupt signal is directly connected to the interrupt terminal. It also provides flexibility such as inputting data to INT.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the relationship between level-based interrupt recognition and its processing routine, FIG. 2 is an explanatory diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing its operation. In the figure, MPU is a microcomputer, CS is an external program memory, DEC is a decoder, and FF is a flip-flop.

Claims (1)

[Claims for Utility Model Registration] A microcomputer that has an external program memory CS and has an interrupt terminal and a terminal that outputs an address ADD for accessing the program memory. a decoder DEC that produces an output when a specific address for reading a program for the decoder is output; and a decoder DEC whose output terminal is connected to the interrupt terminal, and which is set by an external interrupt signal S _IN that interrupts at the signal level, and the output of the decoder 1. An interrupt signal width control circuit comprising a flip-flop FF that is cleared by.