JPH07225691A - Device and method for interrupt processing - Google Patents

Abstract

PURPOSE:To provide an interrupt processor for turning a branching operation until the execution start of a program corresponding to an interruption request to one time by the slight change of a hardware. CONSTITUTION:This processor is provided with a program memory 100 for storing the various kinds of programs, a data memory 120 for storing leading addresses 121 in the program memory 100 of the programs, A storage address 143 for storing the leading address 121 in the data memory 120, a table for making the interruption request 130 and the storage address 143 correspond to each other, an interruption control circuit 140 for receiving the interruption request 130, recognizing the storage address 143 of the program corresponding to the request by referring to the table and reading the leading address 121 of the program stored in the storage address 143 in the data memory 120 and a program counter 110 for holding the read leading address 121.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing device and an interrupt processing method for executing a predetermined process in response to an interrupt request from an external terminal, for example.

[0002]

2. Description of the Related Art In recent years, a digital signal processor (abbreviated as DSP hereinafter) is required to have a high-speed interrupt response (start interrupt processing in a short time after inputting an interrupt request).

That is, the number of devices connected to the DSP, such as data transfer with peripheral devices such as AD / DA converters and communication of control information with the control microprocessor, tends to increase, and these peripheral devices are also increasing. The operating speed (operating frequency) is also increasing. Such control of a plurality of devices and data transfer are executed by an interrupt process inside the DSP, but in that case, by the time the interrupt process starts,
First, an interrupt request is accepted, and then a branch is made to a fixed program memory address X according to the type of the interrupt request.
In general, a predetermined branch instruction held in advance is used to branch to the start address Y of the program corresponding to the accepted interrupt request (for example, "MN 1920 series LSI"). Manual 5-8
Page 9 (1990, published by Matsushita Electronics Industry) ").

The configuration including the flow of signals and the like in the above-mentioned conventional interrupt processing device will be described below with reference to the drawings. FIG. 2 is a configuration diagram showing a configuration of a conventional interrupt processing device.

In FIG. 2, the program memory 200 is shown.
Is a storage means for storing a program to be started by an interrupt request and a branch instruction to the start address in the program memory 200 of the program. The program counter 210 outputs an address for accessing the program memory 200 (hereinafter, this may be referred to as an access address), and the interrupt request signal 2
Reference numeral 30 denotes a signal indicating an interrupt request from an external terminal or the like, and the interrupt control circuit 240 causes the interrupt request signal 23
In response to 0, the interrupt processing start address of the program memory 200 (this is not the start address itself of the program corresponding to the interrupt request signal 230, but the program memory 200 in which a branch instruction for branching to the start address of the program is stored. Address) is output to the data bus 250 described later, and an interrupt instruction, that is, an instruction to write the data on the data bus 250 to the program counter 210 is output.

Here, the interrupt control circuit 240 has a table (not shown) in which the interrupt request signal 230 and the interrupt processing start address in the program memory 200 are associated with each other. Based on the contents of the table, a predetermined interrupt processing start address corresponding to the interrupt request signal 230 is recognized and output.

The address data 242 is an interrupt processing start address output from the interrupt control circuit 240,
The interrupt instruction 245 is an instruction that the interrupt control circuit 240 outputs to a decoder described later, and the control signal 24
6, the interrupt control circuit 240 has a decoder 280 described later.
It is a control signal output to the data bus 250.
Outputs the address data 242 to the program counter 210, the decoder 280 decodes the instruction 205 or the interrupt instruction 245 in accordance with the control signal 246, and the program counter control signal 281 outputs to the program counter 210. This is a control signal for instructing to write data on the data bus 250.

In the interrupt processing device configured as described above, the operation from the receipt of an interrupt request input to the start of execution of the program corresponding to the interrupt request will be described with reference to FIG.

First, the interrupt request signal 230 is input to the interrupt control circuit 240.

The interrupt control circuit 240 outputs to the data bus 250 the address data 242 (interrupt processing start address) which is predetermined according to the type of interrupt request, based on the contents of the above table.

For example, if the interrupt request signal 230 indicates an interrupt "A", it outputs "0" as the address 242, and if it indicates an interrupt "B", it outputs "2" as the address 242.

In this way, the address data 242 are associated with each other depending on the type of interrupt request (this address data 24
2 is generally called an interrupt vector). Since such an interrupt vector is normally set every few addresses (for example, 0 address, 2 address, 4 address, ...), after the address indicated by the address data 242 in the program memory 200, It becomes difficult to store a program consisting of multiple instructions. Therefore, at the address indicated by the address data 242 in the program memory 200, a branch instruction for branching to the head address of the program to be executed by the interrupt request is stored.

At the same time, the interrupt control circuit 240 outputs an interrupt instruction 245 to the decoder 280, and the control signal 24
Activate 6

If the control signal 246 is active, the decoder 280 decodes the interrupt instruction 245 and performs control associated with the start of interrupt processing. That is, by activating the control signal 281, the data on the data bus 250 is written to the program counter 210, and
The value of the program counter 210 before updating is saved in the stack memory (the stack memory and the save configuration to the stack memory are not shown). As a result, branching to the address data 242 (interrupt processing start address) corresponding to the interrupt request signal 230 is executed.

Then, the instruction stored in the address indicated by the address data 242 of the program memory 200, that is, the branch instruction for branching to the head address of the program to be executed by the interrupt request is executed (that is, the branch by the decoder 280). Finally, the execution of the program in response to the interrupt request is started.

[0016]

However, in the case of performing the interrupt processing with the above-described configuration, after the interrupt request is input, the branch to the interrupt vector and the branch to the program to be executed by the interrupt request are performed twice. Eventually, the interrupt processing will start. That is, there is a problem in that a high-speed interrupt response cannot be performed because the branch operation is performed twice regardless of the original interrupt processing.

In view of the problems of the conventional interrupt processing device, the present invention aims to provide an interrupt processing device and method capable of executing a program corresponding to an interrupt request by one branch operation after inputting an interrupt request. And

[0018]

According to a first aspect of the present invention, there are provided a program memory for storing various programs, a data memory for storing storage addresses of the programs in the program memory, a plurality of interrupt requests and the data memory. A table in which the storage address is associated with a storage address is stored, and the interrupt request is received, the storage address of the program corresponding to the request is recognized by referring to the table, and the data in the data memory is stored. It is an interrupt processing device provided with an interrupt control means for reading a storage address of the program stored in a storage address and a program counter for holding the read storage address.

The invention of claim 2 stores various programs in a program memory, stores storage addresses of the programs in the program memory in a data memory, a plurality of interrupt requests and the data memory. A step of associating a storage address in which the storage address is stored as a table, receiving the interrupt request, recognizing the storage address of the program corresponding to the request by referring to the table, and storing the data in the data memory. And a step of reading a storage address of the program stored in the storage address.

[0020]

According to the invention of claim 1, the program memory stores various programs, the data memory stores storage addresses of the programs in the program memory, and the table stores a plurality of interrupt requests and the storage in the data memory. The memory address in which the address is stored is associated.

The interrupt control means receives an interrupt request, and stores the storage address of the program corresponding to the request,
The table is referred to for recognition, the storage address of the program stored in the storage address in the data memory is read, and the program counter holds the read storage address.

According to a second aspect of the present invention, for example, various programs are stored in a program memory in advance, storage addresses of the programs in the program memory are stored in a data memory in advance, and a plurality of interrupt requests and the storage in the data memory are stored. The storage addresses storing the addresses are associated in advance as a table, an interrupt request is received, the storage address of the program corresponding to the request is recognized by referring to the table, and the address is stored in the data memory. The stored address of the stored program is read. As a result, the branch operation until the execution of the program corresponding to the interrupt request can be performed once.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an interrupt processing device according to an embodiment of the present invention.

Here, the main difference from the conventional configuration is that the data memory 120 in which the start address of the program memory 100 of the program to be executed by the interrupt request is stored is stored, and the program corresponding to the interrupt request is accepted. That is, the leading address of the is directly sent to the program counter 110.

In FIG. 1, the program memory 100
Is a storage means for storing a program that starts execution in response to an interrupt request.
0 is for outputting the access address (the program start address 121, etc.) to the program memory 100, and the data memory 120 is the start of the program memory 100 of the program to be executed by the interrupt request stored in the program memory 100. The interrupt control circuit 140 is a storage unit for storing the address 121 (corresponding to the storage address of the present invention).
And the first address 1 in the program memory 100 of a predetermined program whose execution is predetermined.
A table (not shown) associating the storage address 143 in the data memory 120 where 21 is stored.
have.

As a result, the interrupt control circuit 140 is
When the interrupt instruction 130 is received, the contents of the above table are referred to, and in response to the interrupt request, the storage address 143 corresponding to a predetermined program whose execution is predetermined is recognized and the data memory 120 is recognized. Output,
An interrupt instruction 145 and a control signal 146 are output to a decoder 180 described later.

The data bus 150 is the data memory 120.
Data output from the program (start address 121 of the program)
Is output to the program counter 110, and the decoder 180 outputs the instruction 105 output from the program memory 100 or the interrupt instruction 145 output from the interrupt control circuit 140 to the interrupt control circuit 140.
Is a decoder for decoding according to the control signal 146 output by the.

Further, the program counter control signal 181
Is a control signal for instructing to write the data of the data bus 150 to the program counter 110, and the data memory control signal 183 is the data memory 12
This is a control signal for controlling 0 access. Here, the interrupt control means of the present invention is included in the interrupt control circuit 140.

In the interrupt processing device of the present embodiment configured as described above, one embodiment of the interrupt processing method of the present invention is described while describing the operation from the input of an interrupt request to the start of execution of the program corresponding to the interrupt request. , Figure 1
Will be explained.

First, the interrupt request signal 130 is input to the interrupt control circuit 140.

The interrupt control circuit 140 outputs to the data memory 120 a storage address 143 determined in advance according to the type of interrupt request with reference to the above table.

For example, the interrupt control circuit 140 outputs "0" as the memory address 143 if the interrupt request signal 130 indicates the interrupt "A", and outputs "1" as the memory address 143 if the interrupt request signal 130 indicates the interrupt "B". To do. As described above, there is a table in which the storage address 143 is associated with the type of interrupt request.

In the data memory 120, as described above, the head address 12 of the program which is stored in the program memory 100 in advance and is to be executed by the interrupt request signal 130.
Set 1 in advance.

For example, for the interrupt “A”, the start address of the program “A” in the program memory 100 is assigned to the address “0” of the data memory 120, and for the interrupt “B”, the address “1” of the data memory 120 is assigned. The leading address of the program "B" in the program memory 100 is set in the.

At the same time, the interrupt control circuit 140 outputs the interrupt instruction 145 to the decoder 180, and the control signal 1
Activate 46.

Decoder 180 decodes instruction 105 when control signal 146 is not active, that is, when interrupt processing is not performed. If the control signal 146 is active, decode the interrupt instruction 145,
Performs control associated with interrupt processing. That is, by activating the control signal 183, the data memory 120
The data of the address indicated by the memory address 143 (the head address 121 of the program) is output to the data bus 150, and the control signal 181 is activated to cause the program counter 110 to output the data of the data bus 150 (the head of the program). The address 121) is written, and the value of the program counter 110 before updating is saved in the stack memory (the stack memory and the saving configuration in the stack memory are not shown). As a result, the branch to the head address 121 of the program corresponding to the interrupt request signal 130 is executed.

Therefore, after inputting the interrupt request, the program corresponding to the interrupt request can be executed by one branch operation.

Further, since the DSP generally has a program memory and a data memory separately, only a small amount of hardware is added to realize the above effect.

In the above embodiment, the data memory 120 is used.
Although the output data of the above is input to the program counter 110 via the data bus 150, the present invention is not limited to this, and the address data stored in advance in the data memory, that is, the head of the program memory of the program to be executed by an interrupt request Whether the data bus or the like is used does not matter as long as the address can be read and written in the program counter.

Further, although the storage address of the program of the present invention in the program memory has been described as the head address in the program memory 100 of the program in the above embodiment, the present invention is not limited to this. For example, the address in the middle of storing the program. Alternatively, any address such as a rear end address may be used as long as the execution of the program can be started.

Further, although each constituent element in the above embodiment is realized by using a specific hardware circuit, it is not necessarily limited to this, and each constituent element may be realized by software.

[0043]

As is apparent from the above description, the present invention has an advantage that a program corresponding to an interrupt request can be executed by one branch operation after inputting an interrupt request.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an interrupt processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional interrupt processing device.

[Explanation of symbols]

 100 program memory 105 instruction 110 program counter 120 data memory 121 start address 130 interrupt request signal 140 interrupt control circuit 143 storage address (access address) 145 interrupt instruction 146 control signal 181 program counter control signal 183 data memory control signal 150 data bus 180 decoder

Claims (2)

[Claims] 1. A program memory for storing various programs, a data memory for storing storage addresses of the programs in the program memory, and a storage address for storing a plurality of interrupt requests and the storage address in the data memory. A table associated with the interrupt request is received, the storage address of the program corresponding to the request is recognized by referring to the table, and the program stored in the storage address in the data memory is stored. An interrupt processing device comprising: an interrupt control means for reading an address; and a program counter for holding the read storage address. 2. A method of storing various programs in a program memory, a step of storing storage addresses of the programs in the program memory in a data memory, a plurality of interrupt requests and the storage addresses of the data memory being stored. A step of associating the stored memory addresses as a table, receiving the interrupt request, recognizing the memory address of the program corresponding to the request by referring to the table, and storing the memory address in the memory address in the data memory. And a step of reading the storage address of the stored program.