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JPS582046U - Interrupt signal width control circuit - Google Patents

Interrupt signal width control circuit

Info

Publication number
JPS582046U
JPS582046U JP9181681U JP9181681U JPS582046U JP S582046 U JPS582046 U JP S582046U JP 9181681 U JP9181681 U JP 9181681U JP 9181681 U JP9181681 U JP 9181681U JP S582046 U JPS582046 U JP S582046U
Authority
JP
Japan
Prior art keywords
control circuit
interrupt signal
width control
microcomputer
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9181681U
Other languages
Japanese (ja)
Other versions
JPS6234353Y2 (en
Inventor
西川　真二
町田　英和
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP9181681U priority Critical patent/JPS582046U/en
Publication of JPS582046U publication Critical patent/JPS582046U/en
Application granted granted Critical
Publication of JPS6234353Y2 publication Critical patent/JPS6234353Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はレベルによる割込みの認識とその処理ルーチン
の関係を示す説明図、第２図は本考案の一実施例を示す
説明図、第３図はその動作を示すタイムチャートである
。 図中、ＭＰＵはマイクロコンピュータ、Ｃ８は外部プロ
グラムメモリ、ＤＥＣはデコーダ、ＦＦはフリップフロ
ップであ乞。FIG. 1 is an explanatory diagram showing the relationship between level-based interrupt recognition and its processing routine, FIG. 2 is an explanatory diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing its operation. In the figure, MPU is a microcomputer, C8 is an external program memory, DEC is a decoder, and FF is a flip-flop.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プログラムメモリを外部に有しそしてレベル割込みを受
けるマイクロコンピュータの外部割込み信号端子の入力
側にフリップフロップを接続し、また該プログラムメモ
リへ該マイクロコンピュータがアドレス信号を出力する
端子へデコーダを接続し、外部割込み入力信号の前縁で
該フリップフロップをセットしその出力で該マイクロコ
ンピュータに割込みをかけ、また該マイクロコンピュー
タが該プログラムメモリへ該外部側込み入力信号に対応
した特定アドレスを出力したときの該デコーダの出力で
該フリップフロップをリセットｉるようにしてなること
を特徴とする、割込み信号幅制御回路。A flip-flop is connected to the input side of an external interrupt signal terminal of a microcomputer that has a program memory externally and receives level interrupts, and a decoder is connected to a terminal from which the microcomputer outputs an address signal to the program memory; The flip-flop is set at the leading edge of the external interrupt input signal, and its output interrupts the microcomputer, and when the microcomputer outputs a specific address corresponding to the external input signal to the program memory. An interrupt signal width control circuit characterized in that the flip-flop is reset by the output of the decoder.
JP9181681U 1981-06-22 1981-06-22 Interrupt signal width control circuit Granted JPS582046U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9181681U JPS582046U (en) 1981-06-22 1981-06-22 Interrupt signal width control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9181681U JPS582046U (en) 1981-06-22 1981-06-22 Interrupt signal width control circuit

Publications (2)

Publication Number Publication Date
JPS582046U true JPS582046U (en) 1983-01-07
JPS6234353Y2 JPS6234353Y2 (en) 1987-09-02

Family

ID=29886888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9181681U Granted JPS582046U (en) 1981-06-22 1981-06-22 Interrupt signal width control circuit

Country Status (1)

Country Link
JP (1) JPS582046U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49111561A (en) * 1973-02-22 1974-10-24
JPS5672744A (en) * 1979-11-19 1981-06-17 Nec Corp Interruption control circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49111561A (en) * 1973-02-22 1974-10-24
JPS5672744A (en) * 1979-11-19 1981-06-17 Nec Corp Interruption control circuit

Also Published As

Publication number Publication date
JPS6234353Y2 (en) 1987-09-02

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