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JPS62155563A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62155563A
JPS62155563A JP29856585A JP29856585A JPS62155563A JP S62155563 A JPS62155563 A JP S62155563A JP 29856585 A JP29856585 A JP 29856585A JP 29856585 A JP29856585 A JP 29856585A JP S62155563 A JPS62155563 A JP S62155563A
Authority
JP
Japan
Prior art keywords
base
concentration
emitter
portions
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29856585A
Other languages
Japanese (ja)
Inventor
Yoshihiko Nishioka
西岡 善彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP29856585A priority Critical patent/JPS62155563A/en
Publication of JPS62155563A publication Critical patent/JPS62155563A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To provide a semiconductor device capable of withstanding a high voltage against the reverse bias voltage by making the vicinities of corners of the PN junction portion of the base with the emitter high-concentration portions which have a higher impurity on concentration than the other base portions. CONSTITUTION:A P-type impurity is first ion-implanted into an N-type collector 2C to form a base 2B, and then a P<+> type impurity of a higher concentration is ion-implanted again into the vicinities of the corner portions of the PN junction between the collector 2C and the base 2B, forming high-concentration portions 2Ba. Thereafter drive-in thermal diffusion is performed, forming and completing the base 2B. Then, an N<++> type impurity is thermally diffused into the base 2B, forming an emitter 2E. The high-concentration portions 2Ba may also be formed by the thermal diffusion method, if necessary, without being limited to the ion implantation method. The layer resistance rhos of the high- concentration portions 2Ba of a transistor 2 formed in this way is 90-110OMEGA/square, and this value is about 1/3 of the specific resistance rhos of the base 1B of an prior equivalent item, which is 300-350OMEGA/square.

Description

【発明の詳細な説明】 庄  、$lj乞【 本発明は、スイッチング用パワートランジスタ等の半導
体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device such as a switching power transistor.

砲泉些皮1 例えば、テレビジョン受像機のブラウン管の偏向回路等
において鋸歯状波電流を0N1OFFするスイッチング
素子としては、n−p−n接合のトランジスタが使用さ
れている。このようなn −p−n接合のトランジスタ
の構造は、第3図に示すようなものであり、このトラン
ジスタ1は、n型のエミッタIE、p型のベースIB1
n型のフレフタICがそれぞれn−p−n接合されて形
成されており、エミッタIEとベースIBとの間の逆バ
イアス電圧の耐圧値は、通常300〜350V程度であ
った。
For example, in the deflection circuit of a cathode ray tube of a television receiver, an n-p-n junction transistor is used as a switching element for turning a sawtooth wave current ON and OFF. The structure of such an n-p-n junction transistor is as shown in FIG. 3, and this transistor 1 has an n-type emitter IE and a p-type base IB1.
N-type flutter ICs are formed by n-p-n junctions, and the withstand voltage value of the reverse bias voltage between the emitter IE and the base IB is usually about 300 to 350V.

[l イ ″   。[l I     .

このようなトランジスタ1を、前述のようなスイッチン
グ素子として使用した場合には、エミッタIEとベース
IBとの間に高い逆バイアス電圧が加わることが往々に
してあり、前述のように従来のトランジスタ1は逆バイ
アス電圧に対する耐圧値が低いので、高い逆バイアス電
圧によってエミッタIE−ベースIB間の絶縁が容易に
破壊されてしまうという問題があった。
When such a transistor 1 is used as a switching element as described above, a high reverse bias voltage is often applied between the emitter IE and the base IB. has a low breakdown voltage value with respect to a reverse bias voltage, so there is a problem that the insulation between the emitter IE and the base IB is easily destroyed by a high reverse bias voltage.

本発明は、このような従来の問題点に鑑みてなされたも
のであり、逆バイアス電圧に対する高い耐圧値を有する
半導体装置を提供することを目的とするものである。
The present invention has been made in view of these conventional problems, and it is an object of the present invention to provide a semiconductor device having a high breakdown voltage value against reverse bias voltage.

。  ゛ −の 上記目的を達成するため、本発明においては、n−p−
nトランジスタ構造の半導体装置においテ、少すくとも
ベースのエミッタとのpn接合部角部近傍を他のベース
部分より不純物イオン濃度が高い高la度耶とすること
を特徴としている。
.゛ In order to achieve the above object, the present invention provides n-p-
A semiconductor device having an n-transistor structure is characterized in that at least the vicinity of the corner of the pn junction between the base and the emitter is made into a high-la-concentration layer with a higher concentration of impurity ions than the rest of the base.

作ニーー月− 上記構成の半導体装置においては、ベースのエミッタと
の接合部の近傍の不純物イオン濃度か、ベースの他の部
分の不純物イオンl震度より高くなっているので、その
高イオン濃度部の層抵抗ρSが小さくなり、エミッター
ベース間のインピーダンスが小さくなり、エミッターベ
ース間に高い逆バイアス電圧が印加されても、エミッタ
ーベース間の絶縁が破壊されることがなくなる。これは
、エミッターベース間のインピーダンスが小さくなるの
で、その結果逆バイアス時に加わるパワーが以外に少な
くなり、発熱が小さくなるためと考えられる。
In the semiconductor device with the above configuration, the impurity ion concentration near the junction of the base with the emitter is higher than the impurity ion seismic intensity of other parts of the base, so the high ion concentration part The layer resistance ρS becomes smaller, the impedance between the emitter and the base becomes smaller, and even if a high reverse bias voltage is applied between the emitter and the base, the insulation between the emitter and the base is not destroyed. This is thought to be because the impedance between the emitter and base is reduced, which results in less power being applied during reverse bias, and less heat generation.

実−U 第1図に本発明の半導体装置の一実施例としてn−p−
n型パワートランジスタ2の構造を示ス。本実施例のト
ランジスタ2は、従来の通常のトランジスタと同様にn
型のコレクタ2Cにまずp型不純物をイオン注入してベ
ース2Bを形成し、つぎにコレクタ2Cとベース2Bと
のpn接合(コレクタ接合)の角部近傍に、再度より高
濃度のp+型不純物をイオン注入して、高濃度部2Ba
を形成する。その後、押込み熱拡散を行って、ベース2
Bを形成完了する。それから、n廿型不純物をベース2
B中に熱拡散(エミッタ拡散)シて、エミッタ2Eを形
成する。この高に度EilE 2 B aの形成は、も
し必要ならば、イオン注入法に限らず熱拡散法によって
も形成することかできる。
Figure 1 shows an embodiment of the semiconductor device of the present invention.
The structure of n-type power transistor 2 is shown. The transistor 2 of this embodiment has n
First, a p-type impurity is ion-implanted into the collector 2C of the mold to form the base 2B, and then a higher concentration p+-type impurity is again implanted near the corner of the pn junction (collector junction) between the collector 2C and the base 2B. After ion implantation, the high concentration area 2Ba
form. After that, indentation heat diffusion is performed and the base 2
Complete formation of B. Then, the n-type impurity is added to the base 2
Thermal diffusion (emitter diffusion) is performed in B to form an emitter 2E. This highly concentrated EilE 2 Ba can be formed not only by the ion implantation method but also by the thermal diffusion method, if necessary.

斯くして形成されたトランジスタ2の、高71を部2B
aの層抵抗ρSは90〜110Ω/口であり、この値は
、従来の同等品のベースIBの比抵抗ρSが300〜3
50Ω/口であることと比較すると、約1/3である。
The height 71 of the transistor 2 thus formed is located at the portion 2B.
The layer resistance ρS of a is 90 to 110 Ω/mouth, and this value is higher than the specific resistance ρS of the base IB of the conventional equivalent product of 300 to 3
This is about 1/3 compared to 50Ω/mouth.

上記の比抵抗値を有する3種の本発明実施例であるトラ
ンジスタ(実施品1〜3)と、同じく上記の比抵抗値を
有する3種の従来のトランジスタ(比較品1〜3)とに
対して、エミッタE−ベースB間に逆バイアス電圧を印
加して、エミッタ−ベース間の耐圧値を測定した。この
測定は、第2図に示す測定回路TCを用いて行った。こ
の測定回路TCは、スイッチSを端子a側に接続して、
電圧可変の直流電源VEとコンデンサCPとを接続し、
該コンデンサCPを充電した後、スイッチSを端子す側
(ベースa側)に接続し、図示のように接続された供試
トランジスタTのエミッタE−ベースB間に逆バイアス
電圧を印加するものである。測定は、直流電源VEの電
圧値を徐々に上げて行って、供試トランジスタTのエミ
ッタE−ベースB間の絶縁破壊が生じた電圧値を求めた
。この結果を第1表に示す。
Regarding the three types of transistors according to the embodiments of the present invention (implemented products 1 to 3) having the above specific resistance values and the three types of conventional transistors (comparative products 1 to 3) also having the above specific resistance values, Then, a reverse bias voltage was applied between emitter E and base B, and the withstand voltage value between emitter and base was measured. This measurement was performed using the measurement circuit TC shown in FIG. This measurement circuit TC connects the switch S to the terminal a side,
Connect the variable voltage DC power supply VE and the capacitor CP,
After charging the capacitor CP, connect the switch S to the terminal side (base a side) and apply a reverse bias voltage between the emitter E and base B of the transistor under test T connected as shown in the figure. be. The measurement was carried out by gradually increasing the voltage value of the DC power supply VE, and the voltage value at which dielectric breakdown occurred between the emitter E and the base B of the test transistor T was determined. The results are shown in Table 1.

第1表 上記第1表から明らかな如く、本実施例のトランジスタ
のエミッターベース間の逆バイアス電圧に対する耐圧値
はいずれも、従来品に比して約2倍以上であり、本実施
例のトランジスタは優れた耐逆バイアス電圧を有するこ
とが実証された。
Table 1 As is clear from Table 1 above, the withstand voltage values for the reverse bias voltage between the emitter and base of the transistor of this example are approximately twice as high as those of the conventional product, and the transistor of this example It was demonstrated that it has excellent reverse bias voltage resistance.

発IFと従来− 以上の説明より明らかな如(、半導体装置を本発明の構
成とすることによって、エミッターベース間の逆バイア
ス電圧に対する耐圧値を従来の同等品のそれに比して大
きくすることができるので、高い逆バイアス電圧が生じ
る回路に使用することができるようになる。
Source IF and conventional technology - As is clear from the above explanation (by adopting the structure of the present invention for a semiconductor device, the withstand voltage value for the reverse bias voltage between the emitter and base can be increased compared to that of a conventional equivalent product). Therefore, it can be used in circuits where a high reverse bias voltage occurs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すパワートランジスタの
概略断面図、第2図はその逆バイアス特性/1111定
回路図、第3図は従来のパワートランジスタの概略断面
図である。 2・・・パワートランジスタ 2B・・・ベース 2Ba・・・高不純物1度部 2C・・・コレクタ 2E・・・エミッタ
FIG. 1 is a schematic sectional view of a power transistor showing an embodiment of the present invention, FIG. 2 is a reverse bias characteristic/1111 constant circuit diagram thereof, and FIG. 3 is a schematic sectional view of a conventional power transistor. 2...Power transistor 2B...Base 2Ba...High impurity 1 degree part 2C...Collector 2E...Emitter

Claims (1)

【特許請求の範囲】[Claims] n−p−nトランジスタ構造の半導体装置において、少
なくともベースのエミッタとのpn接合部角部近傍を他
のベース部分より不純物イオン濃度が高い高濃度部とし
たことを特徴とする半導体装置。
1. A semiconductor device having an n-p-n transistor structure, characterized in that at least the vicinity of a corner of a pn junction between a base and an emitter is a high-concentration region having a higher impurity ion concentration than the rest of the base.
JP29856585A 1985-12-27 1985-12-27 Semiconductor device Pending JPS62155563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29856585A JPS62155563A (en) 1985-12-27 1985-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29856585A JPS62155563A (en) 1985-12-27 1985-12-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62155563A true JPS62155563A (en) 1987-07-10

Family

ID=17861388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29856585A Pending JPS62155563A (en) 1985-12-27 1985-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62155563A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5644663A (en) * 1992-08-11 1997-07-01 Nisca Corporation Portable image scanner having manual or automatic feed

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5644663A (en) * 1992-08-11 1997-07-01 Nisca Corporation Portable image scanner having manual or automatic feed

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