JPH0828374B2 - Triple diffusion type transistor - Google Patents

Description

The present invention relates to a structure of a triple diffusion type transistor in a semiconductor device.

[Conventional technology]

Conventionally, a triple diffusion type transistor (hereinafter referred to as a T-PNP transistor) used in this type of semiconductor device has the following advantages.

1. The grounded-emitter current amplification factor ( _hFE ) is high.

2. Maximum collector current (hereinafter _referred to as I _CMax ) is large.

3. High cutoff frequency (hereinafter referred to as f _T ).

It is widely used because it has advantages such as the above, and has good complementarity with NPN transistors.

FIG. 3 is a sectional view of a semiconductor chip showing an example of a conventional T-PNP transistor. This T-PNP transistor comprises a first N-type buried layer 2 formed between a P ^- type semiconductor substrate 1 and an N ^- type epitaxial layer 4 formed thereon.
And a second P ⁺ type buried layer 3. Impurity diffusion is sequentially performed from the surface of the reverse conductivity type epitaxial layer on the second P ⁺ -type one conductivity type buried layer 3 so that the one conductivity type collector region, the opposite conductivity type base region and the one conductivity type emitter region are formed. Has been formed.

That is, the first P-type collector region 5 is formed on the P ⁺ -type buried layer 3, and the first P-type collector region 5 is formed.
An N-type base region 7 and a second P ⁺ -type collector region 6a are provided inside.
Are formed.

Further, the N-type base region 7 N ⁺ -type base contact region 9 and the P ⁺ -type emitter region 8a is formed, the second P ⁺ -type collector region 6a are formed a P ⁺ -type collector co tact region . Further, a P ⁺ type insulation isolation region 6 is formed to insulate the periphery of the T-PNP transistor.

Here, the second P ⁺ type buried layer 3, the first P type collector region 5, the second P ⁺ type collector region, and the P ⁺ type insulating isolation region 6 in the first P type collector region 5 are respectively formed. The P ⁺ -type isolation region 6 and the second P ⁺ -type collector region 6 which are continuous,
The P ⁺ type emitter region 8a and the P ⁺ type collector contact region 8b are simultaneously formed. Further, in general, the second P ⁺ -type buried layer 3 is formed with a higher concentration than the first N-type buried layer 2, and the collector saturation voltage of the transistor (hereinafter referred to as V
_{(CE (SAT))} .

[Problems to be Solved by the Invention]

In recent years, in power ICs, as a driver for the power transistor in the output stage of this T-PNP transistor,
Alternatively, it is often applied as a power transistor in an output stage of a pure complementary configuration of an NPN transistor, and particularly, it is remarkable for application to a vehicle power IC. When applying this T-PNP transistor to the output stage of an on-vehicle power IC, 1.I _CMAX is large.

2. V _{CE (SAT)} is small.

3. Large surge voltage resistance.

Etc. are required. Here, 1 and 2 can be realized relatively easily, but 3 is conventionally guaranteed by the breakdown voltage between the emitter base and the short collector of the T-PNP transistor (hereinafter referred to as BV _CES ). _CES needs to be large.

On the other hand, if the base-collector breakdown voltage (hereinafter referred to as BV _CBO) is limited by the avalanche breakdown, approximately equal to the BV _CBO of BV _CES, in order to increase the BV _CES must increase the BV _CBO.

However, in the conventional T-PNP transistor, when the maximum rated voltage is high, the BV _CBO is determined by the reach-through in the vertical path immediately below the N ⁺ type base contact region 9, as shown in FIG. Therefore, in order to obtain the desired BV _CBO , the thickness of the epitaxial layer (hereinafter referred to as t _EPI ) must be increased. However, increasing t _EPI lowers the I _CMAX of the T-PNP transistor,
There is a drawback that it causes an increase in _{CE (SAT)} and increases the element size.

An object of the present invention is to provide a triple diffusion type transistor having a high surge breakdown voltage without lowering I _CMAX , increasing V _{CE (SAT)} and increasing the number of elements.

[Means for solving the problem]

A triple diffusion type transistor of the present invention is formed in a reverse conductivity type epitaxial layer formed on a low concentration one conductivity type semiconductor substrate and in a boundary region between the one conductivity type semiconductor substrate and the opposite conductivity type epitaxial layer. A first reverse-conductivity-type buried layer, a second first-conductivity-type buried layer formed in a boundary region between the first reverse-conductivity-type buried layer and the reverse-conductivity-type epitaxial layer, and the second A triple diffusion type transistor having a one conductivity type collector region, a reverse conductivity type base region and a one conductivity type emitter region which are formed on the one conductivity type buried layer by impurity diffusion in order from the surface of the opposite conductivity type epitaxial layer. A reverse conductivity type base contact region which is provided apart from the reverse conductivity type base region and is formed to have a higher concentration and a shallower concentration than the reverse conductivity type base region, and the first conductivity type A collector region and a part of the reverse conductivity type base region and connected to the second buried layer of the first conductivity type, the collector region having a lower concentration than the emitter region of the first conductivity type. It

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a T-PNP transistor of the first embodiment of the present invention. To facilitate the description of the embodiments of the present invention, description will be made in the order of manufacture.

First, for example, P-type impurity ions are implanted from the surface of the P ⁻ type semiconductor substrate 1 having an impurity concentration of 10 ¹⁴ to 10 ¹⁶ / cm ⁻³ , and the layer resistance (hereinafter referred to as ρ _S ) is 50 to 100 Ω / □. The first N-type buried layer 2 is formed. Next, the second P ⁺ -type buried layer 3 having ρ _S of about 30 to 50 Ω / □ is formed by Bcl ₃ diffusion or B ⁺ ion implantation. Next, the impurity concentration 10 ¹⁴ to 10 ¹⁶ / cm
^-3 N ^- type epitaxial layer 4 is formed.

Next, B ⁺ ions are implanted from the surface of the N ⁻ type epitaxial layer 4 on the second P ⁺ type buried layer 3 so that ρ _S is 500 to 3000Ω.
A first P-type collector region 5a of / □ is formed. Next, for example, due to the diffusion of Bcl ₃ , the second ρ _{S of 7} to 20Ω / □
The P ⁺ type collector region 6a and the P ⁺ type insulating isolation region 6 are formed simultaneously. At this time, the first P ⁺ -type buried layer 3
The type collector region 5a, the second P ⁺ type collector region 6a and the P ⁺ type insulating isolation region 6 are connected to each other.

Next, for example, P ⁺ impurities are ion-implanted so that ρ _S is 10
An N-type base region 7 of about 0 to 300Ω / □ is formed so as to cover the first P-type collector region 5a and have a higher concentration and a shallower concentration than the first P-type collector region 5a. Next, by diffusion of Bcl ₃ , ρ _S
Simultaneously forms the P ⁺ -type emitter region 8a and the P ⁺ -type collector contact region 8b of about 10 to 20Ω / □, that is, the P ⁺ -type emitter region 8a is the first P-type collector region in the N-type base region 7a. It is formed inside 5a so as to have a higher concentration and shallower than the N-type base region 7a, and the P ⁺ -type collector contact region 8b is formed shallowly inside the second P ⁺ -type collector region 6a.

Finally, for example, due to diffusion of Pocl ₃ , ρ _S is 5 to 15Ω
The N ⁺ type base contact region 9 of about / □ is formed outside or in contact with the N type base region 7a. In this embodiment, as compared with the conventional example shown in FIG. 3, the first P-type collector region 5a is formed in the N-type base region 7a and includes the P ⁺ -type emitter region 8a therein. ,
The N ⁺ type base contact 9 is characterized by being formed outside the N type base region 7a.

With this structure, the first P-type collector region 5a
Is formed in the N-type base region 7a, and is formed so as to be included only in the P ⁺ -type emitter region 8a, and the N ⁺ -type base contact region 9 is formed outside the N-type base region 7a. BV _CBO just below the N ⁺ type base contact region 9
Is increasing. That is, since the base region and the first collector region do not exist directly under the N ⁺ type base contact region, the depletion layer is likely to spread, the leak through is relaxed, and the second P ⁺ type buried layer 3, N ⁻ type region is formed. Epitaxial layer and N ⁺
_Withstand voltage in mold base contact area, in other words BV _CBO
Increase.

FIG. 2 is a sectional view of a semiconductor chip showing a T-PNP transistor of the second embodiment of the present invention. This embodiment is the first
The P-type collector region 5b has a structure that includes the P ⁺ -type emitter region 8a therein but does not include a part of the N-type base region 7c. Other than that, it is the same as the first embodiment. Although the above-described embodiments describe only one polarity, the same effect can be obtained even if the polarity is changed.

〔The invention's effect〕

As described above, according to the present invention, the first collector region is formed in the base region or the base region is formed in the collector region, and only the emitter region is formed in the collector region or the base region. Since the N ⁺ -type base contact region is formed outside the base region because there is no base region or first collector region immediately below the base contact region, the depletion layer spreads. The leak through is eased and the breakdown voltage in the second buried layer, the epitaxial layer and the base contact region, in other words, BV _CBO is increased. Also,
Since the PN junction formed by the first collector region and the base region does not exist, the lateral BV _CBO increases, so that the device size can be reduced.

Therefore, the present invention has an effect that a triple diffusion type transistor having a high surge withstand voltage can be obtained without lowering I _CMAX , increasing V _{CE (SAT)} and increasing the number of elements.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing a T-PNP transistor of a first embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor chip showing a T-PNP transistor of a second embodiment of the present invention, FIG. 3 is a sectional view of a semiconductor chip showing an example of a conventional T-PNP transistor. 1 ... P ^- type semiconductor substrate, 2 ... first N-type buried layer, 3
...... Second P ⁺ type buried layer, 4 …… N ^- epitaxial layer,
5, 5a, 5b ... first P-type collector region, 6 ... P ⁺ -type insulation isolation region, 6a ... second P ⁺ -type collector region, 7,7a,
7b ... N-type base region, 8a ... P ⁺ -type emitter region, 9 ...
… N ⁺ type base contact area.

Claims (1)

[Claims] 1. A reverse conductivity type epitaxial layer formed on a low-concentration one conductivity type semiconductor substrate, and a first region formed in a boundary region between the one conductivity type semiconductor substrate and the opposite conductivity type epitaxial layer. Reverse conductivity type buried layer, a second one conductivity type buried layer formed in a boundary region between the first reverse conductivity type buried layer and the reverse conductivity type epitaxial layer, and the second one conductivity type buried layer. A triple diffusion type transistor having a one conductivity type collector region, a reverse conductivity type base region, and a one conductivity type emitter region which are formed on the buried layer in order from the surface of the opposite conductivity type epitaxial layer by impurity diffusion, A reverse-conductivity-type base contact region that is provided apart from the conductivity-type base region and has a higher concentration and a shallower concentration than the reverse-conductivity-type base region, the first-conductivity-type emitter region, and the reverse-conductivity region. Triple diffusion type transistor having said one conductivity type collector region of lower concentration than the one conductivity type emitter region connected to the second one conductivity type buried layer with and a part of the type base region.