JPS6060753A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To increase withstanding voltage without augmenting the area of a substrate by integrally forming an MOS type transistor for increasing withstanding voltage to a planar type transistor. CONSTITUTION:An MOS type transistor 4 is formed integrally between a base and an emitter for a transistor 3 in order to increase the withstanding voltage of a planar type trasistor 3. That is, the planar type transistor 3 is formed by a base region 13, an emitter region 14 and a collector region 12 while a region 15 having the same conduction type as the base region 13 is formed in the collector region 12 as being separated from the base region. A gate oxide film 17 and a gate electrode 18 are formed between the region 15 and the base region 13, thus forming the MOS type transistor 4. The region 15 and the emitter region 14 are connected mutually.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a brainer type transistor, and more particularly to a structure for realizing a high breakdown voltage thereof.

Conventional configurations and their problems Planar transistors are the core circuit elements of bipolar semiconductor integrated circuits (hereinafter simply referred to as ICs). It is necessary to

By the way, the manufacturing process that is the basis of current ICs is n
This is a p-n type planar process, in which an n-type epitaxial layer formed on a p-type silicon substrate is separated into islands, and transistors,
Circuit elements such as resistors and diodes are built in.

In order to increase the breakdown voltage of the transistor, which determines the breakdown voltage of this IC, the impurity concentration of the n-type epitaxial layer is usually lowered and the thickness is increased to increase the thickness of the n-type epitaxial layer.
Increasingly, structural considerations have been made to ensure that the depletion layer extends sufficiently into the epitaxial layer. If this structure is adopted, it will take a long time for the impurity diffusion process to form the isolation region of the transistor, and if the isolation region is formed with a long diffusion length that can penetrate a thick n-type epitaxial layer, the diffusion window The lateral spread from the edge increases,
The area occupied by this insulating isolation region increases, resulting in disadvantages such as an increase in the area of the IC and a rise in cost. To prevent such inconvenience from occurring,
In order to increase the breakdown voltage of the IC, the collector-emitter circuit of transistor 2 is connected between the collector and emitter of transistor 1, as shown in Figure 1, so that when transistor 1 is cut off, transistor 2 is turned on. Countermeasures have been proposed.

This method is based on the collector-base breakdown voltage (BvcB
O) and the collector terminal with the base open. However, there is a relationship between n and a constant determined by the junction. Also, if the resistance between the base and emitter is small, the collector-emitter breakdown voltage BvcER when a resistor is connected between the base and emitter will be BvcB. .

It takes advantage of the property that it approaches . In the circuit shown in the figure, when transistor 1 is in a cut-off state, when transistor 2 is turned on, the resistance between the base and emitter of transistor 1 decreases, so that the collector-emitter breakdown voltage BvcRE of transistor 1 becomes collector-emitter. Base-to-base breakdown voltage Bv
Approach cBO. Therefore, the withstand voltage of the collector terminal is
What would be BvcEo without transistor 2 increases to BVcBO with the addition of transistor 2.

By the way, in order to incorporate such a circuit into an IC, transistors 1 and 2 must be built independently into the IC, which increases the area of the IC by the substrate area occupied by transistor 2. Since the transistor 2 operates in saturation when the transistor 1 is cut off, problems such as an increase in the power consumption of the circuit arise.

Purpose of the Invention The present invention has a structure that can suppress an increase in semiconductor substrate area to the necessary minimum and furthermore can keep power consumption low during operation in order to increase the withstand voltage of a planar transistor. The purpose of the present invention is to provide a semiconductor device with improved performance.

Structure of the Invention A semiconductor device according to the present invention is such that an MO8 type transistor is integrally formed in a planar type transistor, and the two are interconnected. A region having the same conductivity type as the base region is formed, and a gate oxide film and a gate electrode are formed on the surface of the collector region between the region and the base region, and are spaced apart from the base region. The formed region and the five-layer semiconductor region are interconnected, and the structure has four terminals: a collector, a base, an emitter, and a gate. According to this structure, it is only necessary to slightly increase the collector area of the planar transistor in order to fabricate the MO8 transistor, and the increase in the substrate area can be suppressed to the minimum necessary value. MOS) If the transistor is made conductive when the planar transistor is cut off, the first
A circuit operation equivalent to that shown in the figure is performed.

DESCRIPTION OF EMBODIMENTS The semiconductor device of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is an equivalent circuit diagram of the semiconductor device of the present invention, in which a drain source circuit of an MO3O3 type transistor 4 is connected between the base and emitter of a planar type transistor 3 constituting an output stage, and a collector terminal 5 and a base terminal 6. , an emitter terminal 7 and a gate terminal 8.

FIG. 3 is a diagram showing a cross-sectional structure of an IC incorporating a semiconductor device that realizes the circuit shown in FIG. 11, npn composed of an n-type epitaxial island region 12, a p-type base region 13, and an n+ type emitter region 14
The transistor structure is a typical transistor structure of a bipolar IC.

Incidentally, in the semiconductor device of the present invention, in the process of forming the p-type base region 13 into the n-type epitaxial island region 12, the p-type shadow region 16 is simultaneously formed and the Si*2 film 16 covering the silicon substrate is formed. p type base region 13 and p
A gate oxide film 17 and a gate 1 electrode 18 are formed in this part, except for the part located between the shadow areas 15. Furthermore, after forming electrodes 19 to 22 in each area, the emitter electrode 21 and the p shadow are formed. It has a structure in which the electrodes 22 provided in the region 15 are interconnected by a wiring layer 23. In addition, 24 in the figure
2 is an nl type ohmic contact region, and 25 is an insulating film. If this structure is adopted, the p-type base region 13 is placed in the n-type epitaxial island region 12 as a drain region,
An IVIO8 type transistor with the p shadow region 15 as a source region is fabricated together with a play type transistor.

When the semiconductor device of the present invention, which has the above-described structure and is made up of any number of circuits such as those shown in FIG. The substrate potential of the T-type transistor is at a low potential. Therefore, gate terminal 8
If the potential is set to a high potential, the MO8 type transistor 4 is kept in a cut-off state and has no effect on the circuit operation.

On the other hand, when the transistor 3 is cut off, the collector terminal 5 reaches a high potential, and the substrate potential of the MO8 type transistor 4 becomes a high potential. Therefore, by setting the potential of the gate terminal 8 to a low potential, the MO8 transistor 4 becomes conductive, and the base and emitter of the transistor 3 are coupled through a small resistance. Therefore, transistor 3
The breakdown voltage of the collector terminal of is equal to the value of BvcBO.

Furthermore, since the MO8 type transistor 4 is driven by voltage, power consumption is reduced.

Note that in the semiconductor device of the present invention, it is necessary to create an extra region in the collector region that is different from the base region.
Although the area of this reservoir must be secured in advance, the increase in substrate area due to this is much smaller than the increase in area when one transistor is manufactured independently.

Although the present invention has been described above by taking the structure of an IC as an example, the structure of the semiconductor device of the present invention can also be applied to a single transistor.

Effects of the Invention The semiconductor device of the present invention can suppress the increase in substrate area to a very small increase and realize a high withstand voltage of a planar transistor, so that it is possible to suppress a rise in manufacturing costs. Further, since the element which is added to increase the withstand voltage is driven by voltage, the power consumption of this element is significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a conventional circuit diagram proposed for increasing the withstand voltage of a planar transistor, FIG. 2 is an equivalent circuit diagram of a semiconductor device of the present invention, and FIG. 3 is a diagram of a semiconductor device of the present invention. FIG. 2 is a cross-sectional view illustrating the structure of FIG. 1 to 3... Bipolar transistor, 4...
...MO3 type transistor, 6...Collector terminal, 6...-Base terminal, 7...Emitter terminal, 8...Gate terminal, 9... P-type silicon substrate, 1o...n+ type buried region, 11...
... p + type insulation isolation region, 12 ... n type epitaxial island region, 13 ... p type base region, 14 ...
...n+ type emitter region, 15...p shadow region, 16...S 102 film, 17... gate oxide film, 18... gate electrode , 19-22
...Electrode, 23...Wiring layer, 24...
...N+ type ohmic contact area, 25...
...Insulating film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure f Figure 2 Figure 3

Claims (2)

[Claims] (1) A region of the same conductivity type as the base region is formed in the collector region of the planar transistor, separated from the base region, and a gate oxide film and a region of the collector region between the base region and the base region are formed. A gate electrode is formed, and a region formed apart from the base region and an emitter region are interconnected, and a collector,
A semiconductor device comprising four terminals: a base, an emitter, and a gate. (2) The semiconductor device according to claim 1, wherein the collector region is an epitaxial island region of a bipolar semiconductor integrated circuit.