JPH08162469A - Vertical PNP transistor - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] High breakdown voltage and vertical PNP that suppresses the decrease of β (DC current amplification factor) and fT (transition frequency).
Provide a transistor. A P ⁺ type buried layer 4 and a P ⁻ type well 11 are used as a collector region, and an N type well 6 is used as a base region.
^{The ++} diffusion region 9 functions as an emitter region, and the P ⁺ type diffusion region 7 functions as a collector extraction layer. In this way, by making the collector-base junction surface the junction surface of the P ⁻ type well 11 and the N type well 6, a high breakdown voltage can be achieved without widening the base width, and β (DC current amplification factor) and fT can be obtained.
(Transition frequency) can be prevented from decreasing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a vertical PNP transistor, and more particularly to a vertical PNP transistor incorporated in a semiconductor integrated circuit.
Regarding transistors.

[0002]

LS using a bipolar transistor
As I, it is known that an analog circuit is configured by combining an NPN transistor and a PNP transistor, and a vertical PNP transistor has been conventionally proposed in order to achieve high density and high frequency of this analog circuit.

First, a conventional vertical PNP transistor formed simultaneously with an NPN transistor will be described with reference to FIG. As shown in FIG. 4, this vertical PNP transistor has a P − type semiconductor substrate 1, an N ⁻ type epitaxial layer 2 deposited on the semiconductor substrate 1, and an N ⁻ type epitaxial layer formed at a predetermined position on the semiconductor substrate 1. ^{The +} type buried layer 3, the P ⁺ type buried layer 4 formed on the N ⁺ type buried layer 3, the N type well 6 formed in the epitaxial layer 2, and the P type well 6 surrounding the N type well 6. ⁺ and P ⁺ -type diffusion region 7 which is in contact with the type buried layer 4, the P ⁺⁺ diffusion region 9 and N ⁺⁺ type diffusion region 10 formed respectively at predetermined positions of the N-type well 6, P ⁺⁺ diffusion Electrode 2 provided in region 9, N ^{+ +} type diffusion region 10 and P ⁺ type diffusion region 7
1, 22, 23 and an oxide film 20 covering the surface of the epitaxial layer 2 other than the electrodes 21, 22, 23, and the P ⁺ type buried layer 4 serving as a collector region and the epitaxial layer 2 and the N type. The well 6 serves as a base region, the P ⁺⁺ diffusion region 9 serves as an emitter region, and the P ⁺ type diffusion region 7 serves as a collector extraction layer.

The PNP transistor is electrically isolated from other elements by an isolation diffusion region 8 paired with the P ⁺ type preliminary diffusion region 5.

[0005]

However, the vertical PNP transistor having the above structure has the following problems. In order to reduce the operating resistance of the vertical PNP transistor, a high-concentration P ⁺ -type buried layer 4 is provided in the collector region to form an N ⁻ -type epitaxial layer 2 which forms a part of the base region.
Are being deposited.

However, in this structure, at the junction surface between the P ⁺ buried layer 4 and the N ⁻ type epitaxial layer 2, that is, the junction surface between the collector and the base, the impurity concentration of the N ⁻ type epitaxial layer 2 is P ^+. Since the impurity concentration of the buried type layer 4 is lower than that of the buried type layer 4, the depletion layer easily spreads to the P ^{+ +} type diffusion region 9 on the N type well 6 side (base region), and punch-through breakdown occurred at a low voltage. Therefore, it has been difficult to make the breakdown voltage between the collector and emitter regions high.

On the other hand, in order to obtain a high breakdown voltage between the collector and emitter regions, the bottom surface of the P ⁺⁺ type diffusion region 9 and the P ⁺ type burying layer 4 are used.
The distance between and, the so-called base width, must be widened. However, increasing the width of the base causes a decrease in β (DC current amplification factor) and fT (transition frequency), and thus has been restricted in use. In view of the above-mentioned problems, the present invention has a high withstand voltage and β (DC current amplification factor).
And vertical P that suppresses the decrease in fT (transition frequency)
An NP transistor is provided.

[0008]

The present invention has the following constitution in order to achieve the above object. That is, the vertical PNP transistor according to claim 1 is a P ⁻ type semiconductor substrate, an N ⁻ type epitaxial layer deposited on the semiconductor substrate, and an N ⁺ formed at a predetermined position on the semiconductor substrate. Type buried layer and P formed on the N ⁺ type buried layer
And ⁺ -type buried layer, said formed to the surface of the epitaxial layer to reach the buried layer of the P ⁺ -type P ^- -type well, the P ^- -type well in this P ^- greater than type well impurity It is characterized by comprising an N-type well formed at a concentration and a P ⁺⁺ type diffusion region formed at a predetermined position in the N-type well.

[0009]

According to the vertical PNP transistor of the present invention, an N-type well having an impurity concentration higher than that of the P-type well is provided in the P-type well formed so as to reach the P-type buried layer from the surface of the epitaxial layer. Therefore, the junction surface between the collector and the base becomes a junction surface between the P ⁻ type well and the N type well, and the depletion layer generated at the junction surface between the collector and the base is in a lower concentration region, that is, on the P ⁻ type well side. However, it does not extend so much to the N-type well side that is the base region. As a result, punch-through breakdown hardly occurs at a low voltage between the P ⁺ type buried layer and the P ⁺⁺ type diffusion region in the N type well,
The breakdown voltage between the collector and emitter regions can be made high.

Therefore, since a high breakdown voltage can be realized without widening the base width, it is possible to prevent a decrease in β (DC current amplification factor) and fT (transition frequency).

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG. Incidentally, the same reference numerals are given to the same or corresponding portions as in the conventional case. In the vertical PNP transistor of the present invention, as shown in FIG. 1, an N ⁻ type epitaxial layer 2 is deposited on a P ⁻ type semiconductor substrate 1, and an N ⁺ type buried layer is provided at a predetermined position of the semiconductor substrate 1. 3 is formed. A P ⁺ -type buried layer 4 is provided on the N ⁺ -type buried layer 3, and N ⁺
A P ⁺ type pre-diffusion region 5 is formed so as to surround the type buried layer 3.

In the epitaxial layer 2 deposited on the semiconductor substrate 1, a P ⁻ type well 11 reaching the P ⁺ type buried layer 4 is formed.
And a P ⁺ diffusion region 7 which is in contact with the P ⁻ type well 11 and reaches the P ⁺ type buried layer 4, and a P ⁺ type isolation diffusion region 8 which reaches the P ⁺ type preliminary diffusion region 5. . And
An N type well 6 is formed in the P ⁻ type well 11, and a P ⁺⁺ type diffusion region 9 and an N ⁺⁺ diffusion region 10 are formed at predetermined positions in the N type well 6.

P⁺⁺Type diffusion region 9, N⁺⁺Diffusion area 10 and
P⁺Each of the mold diffusion regions 7 has an electrode 2 made of aluminum or the like.
1, 22, 23 are provided. Epitaxial layer 2
The surface of the is covered with an oxide film 20 except for the electrodes 21, 22, and 23.
It is being appreciated. As before, P ⁺ Pair with the pre-diffusion region 5 of the mold
Is electrically isolated from other elements by the isolation diffusion region 8 forming
Have been.

In the vertical PNP transistor of the present invention, P
^{The +} type buried layer 4 and the P ⁻ type well 11 are used as the collector region, the N type well 6 is used as the base region, and the P ⁺⁺ diffusion region 9 is used.
Serves as an emitter region, and the P ⁺ type diffusion region 7 serves as a collector extraction layer. As described above, the collector / base junction surface is the junction surface of the P ⁻ type well 11 and the N type well 6, so that the base has a high withstand voltage without widening, and β (DC current amplification factor) and fT (transition factor). It is possible to obtain a vertical PNP transistor that can prevent a decrease in the oscillation frequency).

Next, a method of manufacturing the vertical PNP transistor of the present invention will be described with reference to FIG. First, FIG.
As shown in (a), P ^- type on N ⁺ -type buried layer 3 formed on a predetermined position of the semiconductor substrate 1 to form a P ⁺ -type buried layer 4, N ⁺ -type buried layer 3 A P ⁺ type pre-diffusion region 5 is formed so as to surround the. Then, the N ⁻ type epitaxial layer 2 is deposited on the surface of the P ⁻ type semiconductor substrate 1. The N ⁺ -type buried layer 3, the P ⁺ -type buried layer 4, and the P ⁺ -type preliminary diffusion region 5 are heated by the heat when the epitaxial layer 2 is deposited.
Of the impurities also diffuses into the epitaxial layer 2.

Next, as shown in FIG. 2B, the P ⁻ type well 1 reaching the P ⁺ type buried layer 4 in the epitaxial layer 2 is formed.
1 is formed, and an N type well 6 is formed in the P ⁻ type well 11 so as to have a predetermined depth. Next, as shown in FIG. 2 (c), P ^- and P ⁺ diffusion region 7 which reaches the P ⁺ -type buried layer 4 in contact with the mold well 11, the P ⁺ -type reaching the pre-diffused region 5 of the P ⁺ -type An isolation diffusion region 8 is formed.

Finally, as shown in FIG. 2D, P ⁺⁺ type diffusion regions 9 and N ⁺⁺ diffusion regions 10 are formed at predetermined positions in the N type well 6. After forming an oxide film 20 on the surface of the epitaxial layer 2, an opening is formed at a predetermined position, and an electrode made of aluminum or the like is formed in each of the P ⁺⁺ type diffusion region 9, the N ⁺⁺ diffusion region 10 and the P ⁺ type diffusion region 7. The vertical PNP transistor of the present invention is completed by forming 21, 22 and 23 by a vapor deposition method or the like.

FIG. 3 shows the impurity profile immediately below the emitter of the vertical PNP transistor of the present invention. As it is apparent from this figure, the junction surface between the collector and base P ^-
The depletion layer extends to the region of lower concentration, that is, the P ⁻ -type well, because it becomes the junction surface between the N-type well and the N-type well.
It does not extend to the mold well side, making punch-through yield less likely to occur.

[0019]

As described above, the vertical PN of the present invention is as described above.
According to P transistor, P-type buried layer is formed so as to reach the P from the surface of the epitaxial layer ^- so are provided N-type well of high impurity concentration than the P-type wells mold well, the collector-base The junction surface between them becomes a junction surface between the P ⁻ type well and the N type well, and the depletion layer generated at the collector / base junction surface is a region having a lower concentration, that is, P.
^- extending the mold well side, does not extend much in the N-type well side is the base region. As a result, punch-through breakdown hardly occurs at a low voltage between the P ⁺ type buried layer and the P ⁺⁺ type diffusion region in the N type well, and the breakdown voltage between the collector and emitter regions can be made high. it can.

Therefore, since a high breakdown voltage can be realized without widening the base width, it is possible to prevent a decrease in β (DC current amplification factor) and fT (transition frequency).

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a vertical PNP transistor of the present invention.

FIG. 2 is an explanatory diagram showing a vertical PNP transistor of the present invention.

FIG. 3 is a drawing showing an impurity profile in a vertical PNP transistor of the present invention.

FIG. 4 is an explanatory diagram showing a conventional vertical PNP transistor.

[Explanation of symbols]

1 P ⁻ type semiconductor substrate 2 N ⁻ type epitaxial layer 3 N ⁺ type burying layer 4 P ⁺ type burying layer 5 P ⁺ type preliminary diffusion region 6 N type well 7 P ⁺ type diffusion region 8 P ⁺ type isolation diffusion region 9 P ⁺⁺ type diffusion region 10 N ⁺⁺ type diffusion region 11 P ⁻ type well

Claims (1)

[Claims] 1. A P-type semiconductor substrate, an N-type epitaxial layer deposited on the semiconductor substrate, an N-type buried layer formed at a predetermined position of the semiconductor substrate, and the N-type epitaxial layer. A P type buried layer formed on the buried layer, a P type well formed to reach the P type buried layer from the surface of the epitaxial layer, and the P type well in the P type well. A vertical PNP transistor comprising an N-type well formed with an impurity concentration higher than that of the well and a P-type diffusion region formed at a predetermined position in the N-type well.