JP3068510B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bipolar process without epitaxial growth, and more particularly to a lateral PNP transistor.

[0002]

2. Description of the Related Art In a conventional process without epitaxial growth, when forming a collector layer of an NPN transistor,
In order to increase the withstand voltage between the collector and the emitter (that is, to extend the depletion layer), it was necessary to reduce the N-type impurity concentration. Furthermore, to lower the collector resistance,
It was necessary to insert a high concentration N-type buried layer. The upper portion of the collector layer of such an NPN transistor is required to be formed at a low concentration, and impurities are implanted by diffusion from the surface. Also, ion implantation does not provide good concentration control. Therefore, the upper portion of the collector layer is formed to be dense near the surface and become thinner toward the inside.

Here, the mobility of the PNP transistor is about three times as large as that of the NPN transistor, because the carrier is a hole, compared to the case where the carrier is an electron.
It is formed in a manner associated with the N transistor. That is,
The characteristics of the NPN transistor have priority. Therefore, horizontal P
Since the concentration of the base layer (that is, the collector layer of the NPN transistor), which is a term for determining the current amplification factor of the NP transistor, is determined by the NPN transistor,
At present, the current amplification factor does not increase more than about 50 times.

Here, since the collector layer and the emitter layer of the lateral PNP transistor are made of the base layer of the NPN transistor (the base layer of the NPN transistor is thinly formed near the surface to improve the characteristics),
The effective portion of the base layer of the P-transistor also has a high concentration near the surface. If the concentration of the base of the effective portion of the transistor can be reduced, the recombination current of minority carriers is reduced, and the current amplification factor is improved.

[0005]

In the above-mentioned conventional example,
The emitter layer and the collector layer are formed shallowly due to the diffusion condition of the NPN transistor which is prioritized in characteristics, and the effective base layer becomes shallow and dense. Therefore,
There is a problem that the current amplification factor of the lateral PNP transistor in the conventional bipolar process without epitaxial is only about 50 times. Usually, 100 times or more is desirable.

In view of the above, an object of the present invention is to solve the above-mentioned problem, thereby making it possible to reduce the power consumption of a semiconductor by improving the current amplification factor of a lateral PNP transistor, and thereby achieving high integration by reducing the number of elements. It is another object of the present invention to provide a semiconductor device capable of increasing the frequency of the amplification limit and increasing the speed.

[0007]

In order to achieve the above object, a semiconductor device of the present invention is a lateral PNP transistor having a semiconductor substrate of the first conductivity type. A first second conductivity type impurity region formed, a second second conductivity type impurity region overlapping with the bottom of the first second conductivity type impurity region and formed at a deep position; A first conductivity type impurity region and a second first conductivity type impurity region formed in and near the surface of the second conductivity type impurity region, wherein the first first conductivity type impurity region; The first depth of the first conductivity type impurity region is defined as the depth of the overlapping portion of the first second conductivity type impurity region and the second second conductivity type impurity region .
The concentration of the second conductivity type impurity region is high near the surface,
It is characterized in that it becomes thinner as it goes to .

Further, the first conductive type semiconductor substrate and the first conductive type
Preferably, the first and second second conductivity type impurity regions are P-type, and the first and second second conductivity type impurity regions are N-type .

Furthermore, it is preferable that the first and second second conductivity type impurity regions are used as base regions, one of the first and second first conductivity type impurity regions is used as an emitter region, and the other is used as a collector region. .

Furthermore, it is preferable that the depth of the first first conductivity type impurity region and the depth of the second first type impurity region are adjusted by the length of the heat treatment time.

The semiconductor device of the present invention is particularly suitable for use in a horizontal PNP.
By pushing the collector layer and the emitter layer down to a portion where the base layer of the transistor is just thin and reducing the concentration of the effective base layer, the recombination of minority carriers is reduced and the current amplification factor is improved.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 to 4 show a semiconductor device of the present invention, and FIGS. 5 to 7 show conventional semiconductor devices. The present invention will be described in comparison with a conventional example.

First, FIG. 1 will be described in comparison with FIG. FIG. 1 is a schematic diagram showing a configuration of an embodiment of a semiconductor device of the present invention. This device includes a collector electrode 4a, a base electrode 5, and an emitter electrode 4b. In manufacturing the chip shown in FIG. 1, first, N-type diffusion layers 2 and 3 are formed on a P-type silicon substrate 1 (about 500 Ω / □). Next, the collector layer 4a and the emitter layer 4 of the lateral PNP transistor
b and P ⁺ type (about 100Ω / □). At this time, the heat treatment is performed for a longer time than in the related art, thereby pushing the boundary between the N-type diffusion layers 2 and 3. Next, an N ⁺ diffusion layer 5 as a base contact is formed (about 100Ω / □). As can be seen by comparing this figure with FIG. 5, which is a conventional semiconductor device, the feature of the present invention is that the collector layer and the emitter layer are deeply pushed.

Next, FIG. 2 will be described in comparison with FIG. FIG. 2 is a density profile along the line AA ′ in FIG.
FIG. 6 is a density profile along the line BB ′ in FIG. With reference to these figures, how far the collector layer 4a and the emitter layer 4b are pushed will be described below. As described above, the collector layer 4a and the emitter layer 4b of the present invention have been pushed down to the portion of the base layer 5 where the concentration profile is thin. That is, it is near the boundary between the N-type diffusion layers 2 and 3.

Next, FIG. 3 will be described in comparison with FIG. FIG. 3 shows a current path of the semiconductor device of the present invention, and FIG. 7 shows a current path of a conventional semiconductor. As described above, according to the present invention, the thinner part of the base layer in the current path becomes the effective base layer, and the base current indicated by the thin arrow C in FIG. That is, a current path having a high current amplification rate becomes dominant.

FIG. 4 is a graph showing the characteristics of the collector-emitter depth versus the current amplification factor of the present invention. The vertical axis shows the current amplification factor (times), and the horizontal axis shows the depth Xj (μm). As described above, the collector layer 4a and the emitter layer 4
In the case of the characteristic shown in this figure, the depth of b is effective in the range of about 0.48 μm to 0.52 μm when the current amplification factor is allowed to be 10% of the maximum value in consideration of manufacturing variations.

[0017]

As described above, according to the present invention, in the lateral PNP transistor in the bipolar process without epitaxial layer, the collector layer and the collector layer are thinned to the point where the concentration profile of the base layer is thin (the boundary between the N-type diffusion layers 2 and 3). By pushing in the emitter layer, the concentration of the effective base portion was changed, and the current amplification factor was improved to about 2.5 times as compared with the conventional case.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a diagram showing a density profile along the line AA ′ in FIG. 1;

FIG. 3 is a diagram illustrating an amplifying operation of the lateral PNP transistor of the present invention.

FIG. 4 is a diagram showing a collector-emitter depth vs. current gain characteristic of the present invention.

FIG. 5 is a plan view showing a configuration of a conventional semiconductor device.

FIG. 6 is a diagram illustrating a density profile along line BB ′ in FIG. 5;

FIG. 7 is a diagram for explaining an amplifying operation of a conventional lateral PNP transistor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 P-type semiconductor substrate 2 N-type diffusion layer 3 N-type diffusion layer 24 P ⁺ -type diffusion layer 4 a Collector electrode 4 b Emitter electrode 5 N ⁺ -type diffusion layer

Continuation of the front page (56) References JP-A-63-93154 (JP, A) JP-A-63-3459 (JP, A) JP-A-63-136669 (JP, A) JP-A-53-60179 (JP, A) , A) JP-B-46-41653 (JP, B1) JP-B-51-6509 (JP, B1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/33-21/331 H01L 29/68-29/737 H01L 21/8222-21/8228 H01L 21/8232 H01L 27/06-27/06 101 H01L 27/08-27/08 101 H01L 27/082

Claims (4)

(57) [Claims] 1. A lateral PNP having a semiconductor substrate of a first conductivity type.
A semiconductor device for a transistor, comprising: a first conductive type semiconductor substrate formed near a surface of the first conductive type semiconductor substrate.
A second conductivity type impurity region, a second second conductivity type impurity region overlapping with a bottom of the first second conductivity type impurity region and formed at a deep position, and the first second conductivity type. A first first-conductivity-type impurity region and a second first-conductivity-type impurity region formed in and near the surface of the first-conductivity-type impurity region. 2
First conductivity type impurity region and a depth, wherein the first second-conductive type impurity region, the depth Satoshi of the overlapping portion of the second second-conductivity type impurity regions, the first of the second conductivity type impurity Territory
The density of the area is dense near the surface,
The semiconductor device characterized by the. 2. The semiconductor substrate of the first conductivity type, and the first and second impurity regions of the first conductivity type are P-type, and the first and second impurity regions of the second conductivity type are N-type . The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein the first and second second conductivity type impurity regions are used as base regions, one of the first and second first conductivity type impurity regions is used as an emitter region, and the other is used as a collector region. The semiconductor device according to claim 2, wherein: 4. The method according to claim 1, wherein the depth of said first first conductivity type impurity region and said second first type impurity region are adjusted by the length of heat treatment. The semiconductor device according to any one of the above.