JPS59189671A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To obtain a device including a P-N-P transistor characterized by high withstand voltage, a large current amplification factor, and a large cut-off frequency, by completely depleting the amount of impurities in a P type collector region when reverse bias having a specified value or more is applied across a base and a collector. CONSTITUTION:A P type collector region 22 is embedded in an N type region 6 and connected to a collector electrode 13 by a P type collector electrode extracting part 8 having high impurity concentration. The collector electrode extracting part 8 is formed in a ring shape, and a base region 9, which is separated from the N type region 6, is formed. An N<+> base region 21 is formed in the region 9. A P<+> emitter region 10 is formed in the base region 21. The regions 21 and 10 are connected to a base electrode 14 and an emitter electrode 15, respectively. Owing to the presence of the N<+> region 21, a depletion layer from a base-collector P-N junction is expanded to the P type collector region 15. The impurity concentration of the P type collector 15 is completely depleted when about 20V is applied across the base and the collector.

Description

[Detailed Description of the Invention] The present invention relates to a semiconductor device VC, particularly a vertical type PI'JP).
The present invention relates to a structure VC of a semiconductor integrated circuit including a transistor assembly.

Conventionally, in semiconductor integrated circuits, both NPN) transistors and VCPNP transistors have been generally used, and a vertical 1'NP structure is available as a structure of PNP) transistors.

For example, FIG. 1 shows a known vertical PNP structure.

An N-type region 2 with a high impurity concentration is formed in a P-type semiconductor substrate 1 and buried with an N-type layer 3&C formed by epitaxial growth VC. Next, there is an insulating buried layer 4 that electrically isolates the transistors.
The entire high impurity concentration P type region 5 formed at the same time is buried by a second epitaxially grown N type layer 6 VC. Further, an electrode is taken out from the collector region 5 by a P-type region 8 with a high impurity concentration formed at the same time as the insulating region 7, and the P-type region 8 is separated from the N-type base region 9k as an annular structure. Furthermore, a P-type emitter 10 with a high impurity concentration and an N-type base contact portion 11 with a high impurity concentration are formed in the base region 9. Finally, holes are formed in the oxide film VC on the surface, and collector, base and emitter electrodes 13, 14 and 15 are formed.

The problem with such a vertical PNP structure is that a transistor with a high breakdown voltage has a low gain. Ding, H'
Reverse breakdown voltage of V L'V All conventional vertical PNPO
If you try to make it high with the BO0FiO structure, the collector-based P-N
It is necessary to reduce the impurity concentration of the base region 9 in the junction and further increase the width WB=i of the base region 9 to prevent the depletion layer of the bottom-heath I'-N junction from reaching the emitter region 10. there were. With this kind of structure, the base was wide, so there was a drawback that the substream amplification factor and the boost frequency were low. Since the depletion layer from the collector-base junction reaches the emitter and prevents the transistor from performing the punch-through phenomenon, it is also known to form the base layer 12' with a high impurity concentration as shown by the dotted line in FIG. In order to achieve a reverse breakdown voltage of 100V or more, the thickness of the base must be several micrometers or more, and the above-mentioned drawbacks cannot be avoided.

An object of the present invention is to provide a semiconductor device including a PNP transistor that has a high breakdown voltage, a large current amplification factor, and a high cutoff frequency.
A semiconductor substrate and an N-type region electrically decomposed by VC, and this N-type region
A P-type collector region embedded in the mold region, a P-type collector electrode extraction portion with a high impurity concentration from which the substrate surface VCC electrode is taken out from the P-type collector region, and an N-type region above the P-type collector region. The formed N-type base region with high impurity concentration and the P-type base region with high impurity concentration formed in the base region.
The amount of impurity in the P type collector region, including the type emitter, is configured to be completely I/il: depleted when a reverse bias of a predetermined value or more is applied between the base and the collector.

Therefore, if the voltage applied to the collector is below a predetermined value, P
Holes injected from the emitter (P type with high impurity concentration) to the N (type with high impurity concentration) base VC pass through the base by drift and diffusion and reach the P type collector. The holes that have reached the collector are extracted to the outside through the P+ collector electrode extraction portion where VC flows in the P type collector region parallel to the substrate. At this time, the P-type collector is not depleted and current flows as an ohmic current VC. On the other hand, when the voltage applied to the collector is higher than a predetermined value, the holes injected from the P emitter to the N heir pass through the base and reach the collector V. At this time, the collector region is a depletion layer, and one collector current flows through the depletion layer. After flowing parallel to the substrate, the P+ collector electrode is taken out to the outside. This operation is expressed as an equivalent V as a series connection of a l'NP) transistor and a t'-ch junction FET. You can do it. In other words, it is equivalent to the channel part of a P-ch junction FET in which the collector vC of a P-type collector region buried in the N-type head region is connected to the collector vC@column vc of a NP transistor. -1fcP The collector electrode lead-out portion can be viewed isometrically as a drain, and the base as a gate. Therefore, if the p (pinch-off voltage) of the above FET is selected to be below the collector base breakdown voltage of the transistor (P N l' ) as the predetermined value mentioned above, when a high potential of 79 or more is applied to the collector external terminal, the voltage exceeding hVpffi will be It is held between the source and drain of.

Pinch-off voltage V is determined by the vertical structure of this semiconductor device, that is, the impurity concentration of the P-type collector region and N-type base region, and the VC depth.The reverse breakdown voltage is determined by the pinch-off voltage of the buried collector region. However, since the pressure is determined by one pressure with the N-type region outside the VC buried collector region, a high breakdown voltage PNP transistor can be obtained regardless of the base width VC.

According to such VC and uninvented VC, is it a transistor with high internal pressure without deteriorating frequency characteristics or current amplification factor? A semiconductor device including the present invention is provided.

Embodiments of the present invention will be described in detail with reference to the VC diagram below.

FIG. 2 VC shows an embodiment of the present invention. Shown in Figure 2;
gPNP) transistor has an entire N-type buried region 2 with a high impurity concentration at the bottom. This region 2 is located in an N-type island region 3 separated by a P-type substrate 1 and an insulating region 4 VC.
embedded. A second insulating region 7 is introduced in which a VCP-type non-contour is introduced into the surface portion of the island-like region 3 and connected to the insulating region 4V.
By forming four N-type regions 6 formed by V, an fcP-type collector region 22 embedded in the region 6 is formed. Note that regions 3 and 6 are formed by epitaxial growth.

The P-type collector region 22 is connected to the collector electrode 13 by a P-type collector electrode lead-out portion 8vc with a high impurity concentration. A base region 9 separated from the N-type region 6 is formed by forming an annular VC with eight collector electrode lead-out portions. Inside the area 9, the N Heath head mount 21 is of the shape J5'i,
A P+ emitter region 10 is formed inside the base region 21, and each has a base electrode 14 and an emitter electrode 15.
VC connected O Figure 2 VC shown 1. The impurity concentration distribution applied to the center of the emitter of a transistor can be explained by referring to Figure 3.
Due to the existence of the N base region 21, the depletion layer from the base-collector PN junction spreads toward the P-type collector region 15 at zero, and the impurity concentration of the P-type collector 15 is approximately 20 V applied between the base and the collector. It is designed to completely deplete VC when

Therefore, the PNP transistor in FIG. 2 is connected to the VC1 region 10 as shown in FIG. Areas 9, 21 and 22'
e P and N as the emitter, base and collector respectively
P) A transistor and a junction FET having a source and channel in region 22', a gate in region 9 and 21, and a drain in region 8 can be represented as being connected in series. The depletion of the channel region of the junction WFET, that is, the P-type collector region, is large at the outer periphery of the VC and P-type collector regions, as indicated by the dotted line 20 in FIG. Pinch-off occurs at the outer periphery in response to a voltage higher than the emitter 1o.Even if the voltage is increased beyond this point, the pinch-off point will only spread to just below the emitter 1o, and the P-type collector region 22 and base region (9 , 21) will not exceed the pinch-off potential Vp?+-.

Therefore, the base concentration distribution and base width are Lvag.

20V'! For example, if the pace width is 1 μm and Th is VC, then fT = 2ooMH
2. A PNP transistor with hF8=100 or so can be obtained. Further VC, LVo as a whole transistor
F.

Since the collector region 22 is pinched off, the impurity concentration of the VCN type region 6 is sufficient. The condition for pinch-off of the collector region 22 is 1× per unit cubic senna meter.
Impurity concentration of 1012 atoms or less and a radiation V of 4 to 5 times or more
The ratio of the length to C is required, and in the non-example, the average impurity concentration of the entire collector region 22 IX1lX10l53, 5
Formed with a thickness of μm and a length of 201xr1, and the area 6
f4×10"cm-"
0v or more was obtained. Also, Lvo one. Since it is determined by the pinch-off characteristic of the P-type collector region and is not related to the thickness of the N-type regions 3 and 6, it can be made thinner, and the lateral spread of each impurity concentration caused by VC in the fabrication of semiconductor devices can be reduced. Therefore, it is also effective in increasing the degree of integration.

As explained above, by using the VC-inventive VC twist, a semiconductor device including a high-voltage and high-performance (NP) transistor can be obtained.

Although the present invention is used as a part of the epitaxial layer as a whole space region, it can also be applied to a triple diffusion type P I'J P transistor, and the conductivity types of all the regions may be changed.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventionally known vertical PNP transistor.
Fig. 2 is a cross-sectional view of a PNP transistor which is an embodiment of the present invention, Fig. 3 is a diagram showing the depth and impurity concentration of the PNP transistor immediately below the emitter of the VC according to the embodiment of the present invention, and Fig. 4 is a diagram showing the impurity concentration of the PNP transistor according to the embodiment of the present invention. FIG. 1 is a circuit diagram equivalently representing a semiconductor device according to the present invention. 1 is a P-type substrate, 2trr, N buried region, aUN-type island-shaped head region, 4 is the lower part of the P-type insulating region, 5 is the P-type collector region, 6 is the upper part of the N-type island-shaped region, 7 is the The upper part of the P type insulating region, 8 is the P type collector electrode extraction part, 9 is the N type base region, 10 is the P vine area, 11 is the N heath electrode extraction part, 120 is the N base area, 13 is the collector electrode , 14 is the base electrode, 15 is the emitter electrode, 20 is inside the P-type collector region (the end of the expanded depletion layer).

Claims (1)

[Claims] 1. A semiconductor device comprising a transistor in which at least a portion of a collector region is depleted in the thickness direction when a full reverse bias voltage of a required value or more is applied between a base and a collector.