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JPS6196541U - - Google Patents

Info

Publication number
JPS6196541U
JPS6196541U JP1984181719U JP18171984U JPS6196541U JP S6196541 U JPS6196541 U JP S6196541U JP 1984181719 U JP1984181719 U JP 1984181719U JP 18171984 U JP18171984 U JP 18171984U JP S6196541 U JPS6196541 U JP S6196541U
Authority
JP
Japan
Prior art keywords
substrate
resin layer
integrated circuit
circuit device
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984181719U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984181719U priority Critical patent/JPS6196541U/ja
Publication of JPS6196541U publication Critical patent/JPS6196541U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例をしめす構造断面図、
第２図ａ，ｂは要部をしめす構造断面図であり、 １は金属基板、２は第１の樹脂層、３は絶縁基
板、４，６は電子部品、５は金属片、７は第２の
樹脂層、８，９は絶縁片、１０は２の樹脂部であ
る。 Figure 1 is a structural sectional view showing an embodiment of the present invention;
Figures 2a and 2b are structural cross-sectional views showing the main parts; 1 is a metal substrate, 2 is a first resin layer, 3 is an insulating substrate, 4 and 6 are electronic components, 5 is a metal piece, and 7 is a first resin layer. 2 is a resin layer, 8 and 9 are insulating pieces, and 10 is a resin part 2.

Claims (1)

【実用新案登録請求の範囲】 (1) 金属基板上に複数個の絶縁片を混入した第
１の樹脂層を設け、該第１の樹脂層上に電子部品
を配設した基板を接置固定し、更に第２の樹脂層
により被覆したことを特徴とする混成集積回路装
置。 (2) 基板として半導体素子を固着した金属片及
び信号回路部品を配設した絶縁基板を用いた実用
新案登録請求の範囲第(1)項の混成集積回路装置
。[Claims for Utility Model Registration] (1) A first resin layer mixed with a plurality of insulating pieces is provided on a metal substrate, and a substrate on which electronic components are arranged is fixed on the first resin layer. A hybrid integrated circuit device characterized in that the hybrid integrated circuit device is further coated with a second resin layer. (2) A hybrid integrated circuit device as set forth in claim (1) for utility model registration, which uses as a substrate a metal piece to which a semiconductor element is fixed and an insulating substrate on which signal circuit components are arranged.
JP1984181719U 1984-11-30 1984-11-30 Pending JPS6196541U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984181719U JPS6196541U (en) 1984-11-30 1984-11-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984181719U JPS6196541U (en) 1984-11-30 1984-11-30

Publications (1)

Publication Number Publication Date
JPS6196541U true JPS6196541U (en) 1986-06-21

Family

ID=30739260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984181719U Pending JPS6196541U (en) 1984-11-30 1984-11-30

Country Status (1)

Country Link
JP (1) JPS6196541U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5797634A (en) * 1980-12-11 1982-06-17 Canon Inc Hybrid integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5797634A (en) * 1980-12-11 1982-06-17 Canon Inc Hybrid integrated circuit

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