JPS6195652A - Digital tone generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a digital tone generating circuit, and relates to a technique effective for use in, for example, a push-button dual-tone telephone.

[Background technology]

Conventionally, digital tone generators used in push-button dual-tone telephones have been known (
For example, AM I (AMf!l?IcAN MIC
(See pages 4 to 14 of the product catalog "S 2559 A/B/C/DJ, Digital Tone Generator" published by RO5YSTEMS INC) in January 1979).

In order to accurately form a plurality of desired tones (frequency signals of 697Hz to 1633Hz), conventional digital tone generators calculate the number of steps constituting one cycle of a staircase-like tone and the least common multiple of these multiple frequencies. For example, a reference frequency signal (3,579545 MHz) formed by a color burst crystal oscillation circuit used in a color television receiver is used. , which hinders lower power consumption and lower operating voltage.

[Purpose of the invention]

An object of the present invention is to provide a digital tone generating circuit that achieves low power consumption and low operating voltage.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by switching the count value of a program counter circuit that counts reference frequency signals in accordance with a key input signal to a correction value at a specific step, a step-wave tone signal having a desired frequency is formed.

〔Example〕

1st B! ! 2 shows a block diagram of an embodiment of a digital tone generating circuit according to the present invention.

Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using a known semiconductor integrated circuit manufacturing technique. This embodiment circuit forms four types of tone signals on the common-row side for the bush buttons, although this is not particularly limited.

The reference frequency signal φ is configured by a reference frequency oscillation circuit (not shown). Although not particularly limited, this reference frequency oscillation circuit is configured by a ceramic oscillation circuit using a ceramic resonator, and generates a relatively low frequency signal, for example, 400 KHz.

This reference frequency signal φ is frequency-divided by the next program counter circuit C0NT. That is, each frequency division stage output 2 to 2 of the counter circuit C0NT receiving the reference frequency φ
32 is input to the second ROM (read only memory). This ROM is constituted by a vertical mask ROM in which enhancement type MOS FETs are formed at the intersections of a grid, which are indicated by circles. At the intersection of other grids,
Although not shown, a depletion type MOSFET is formed. Each of the above MO3FETs is connected in series along a horizontal grid. The gate of the enhancement type MOS FET connected in series with this horizontal grid receives a key input signal 1 generated by a key (button).
~4 is supplied. The key input signals 1 to 4 are supplied to select two grids, respectively. One end of each of the series MOSFETs arranged in the grid is commonly connected to a ground potential point of the circuit. Further, the other end of the series MOSFET is shared and used as an output.

Although not particularly limited, a load MO3FETQI is provided between this output point and the power supply voltage Vcc, which is activated by a bias voltage Vref.

The output of the ROM is connected to the inverter circuit IV2. IV
3 to the input of the flip-flop circuit F1. The flip-flop circuit F1 holds the output signal of the ROM in synchronization with the reference frequency signal φ by supplying the reference frequency signal φ to its clock terminal.

On the other hand, the key input signals 1 to 4 are NOR (N).

R) Supplied to the input of gate circuit G1. The output of this NOR gate circuit G1 is connected to an inverter circuit IV on the one hand.
It is supplied to one input of a NAND gate circuit G2 via I. The output Q of the flip-flop circuit F1 is supplied to the other input of the Nant gate circuit G2. The output of this AND gate circuit G2 is supplied to the reset terminal of the counter circuit C0NT.

As a result, the counter circuit C0NT is controlled by the RO
It operates as a program counter according to the write information of M.

Now, when none of the key inputs 1 to 4 are input,
All the signals are set to logic "0". This causes the output of the gate circuit G1 to become logic "1", so the output of the inverter circuit IVI is set to logic "0".
Since the output of the gate circuit G2 is set to logic "1", the counter circuit C0NT remains in the reset state,
Its counting operation has been stopped.

When one of the key inputs 1 to 4 is supplied, the output of the gate circuit G1 becomes logic "1", one input of the gate circuit G2 becomes logic "1", and the output is set to logic “0”.

As a result, the counter circuit C0NT is released from the reset state and starts counting the reference frequency φ.

By the above key input and the outputs 2 to 32 of the counter circuit C0NT, the enhancement type MO
When all S FETs are turned on, their outputs are set to logic "0".

Therefore, the output Q of the flip-flop circuit F1 is changed from logic "1°" to logic "O", so gate circuit G2
The output of C0NT becomes logic "L" and resets the counter circuit C0NT. By resetting the counter circuit C0NT, the output of the ROM becomes logic "1", so the flip-flop circuit F1 becomes logic "61" again in synchronization with the next clock φ, and the output of the ROM becomes logic "61" again in synchronization with the next clock φ.
Divide the reset state of NT by g. By repeating this, a frequency-divided output of the reference frequency signal φ is obtained from the output Q of the flip-flop circuit F1 in accordance with the frequency division ratio (count value) selected by the key input.

Thereby, four types of variable frequency division outputs can be obtained according to the above key inputs.

In order to form a stepped tone signal based on the pulse signal formed by such minute-minute operation, the output pulse of the flip-flop circuit F1 is frequency-divided by 1/2 by the flip-flop F2, and the pulse duty is adjusted. 5
The pulse signal is converted to 0%. This pulse signal A is supplied to the Johnson counter circuit J-CONT.

The output of the NOR gate circuit G1 is supplied to the reset terminal of this Johnson counter circuit J-CONT.

As a result, when no key input is made, the operation of this counter circuit J-C0NT is stopped.

In this embodiment, two types of division ratios are assigned to each of key inputs 1 to 4, respectively.

Although not particularly limited, the above Johnson counter circuit J-
The lowest bit output and the most significant bit output of CONT are supplied to the exclusive OR circuit EX, which corresponds to the peak value of the staircase wave tone output No. 4R OUT formed by the D/A conversion circuit D/RI, which will be described later. In this step, the frequency division ratio is switched. Therefore, the output of the exclusive OR circuit and the f inverter circuit I
The inverted signal formed by V4 is the key input 1 above.
~4 grids each with two grids (series M
MOS that selects one side of O5FET in a complementary manner
FET is placed.

The tone generation operation of this embodiment circuit will be explained with reference to the waveform diagram in FIG.

As described above, in response to one key input, a pulse A is generated according to the divided output of a preset reference frequency.

This pulse A causes the Johnson counter circuit J-CO to
NT, like outputs B to C, changes every time the pulse A changes (
A pulse signal delayed by half a cycle is formed. As a result, in each half cycle, the bit increases by 1 bit starting from the least significant bit, and after reaching the peak value, it decreases, so the D/A converter circuit D/2 treats the half cycle of the pulse A as one step. Convert to a staircase wave analog signal.

The time of one step of the staircase wave is a fixed time that is an integral multiple (frequency division ratio) of the reference frequency φ. By setting this time according to key inputs 1 to 4, it is possible to form analog signals OUT in a staircase wave state with different periods (frequencies).

However, if one type of frequency division ratio is used for each key input as in the past, it is necessary to use a high reference frequency signal according to the least common multiple thereof. On the other hand, in this embodiment, the Johnson counter circuit J
-CONT least significant bit output B and most significant bit signal C
At the step where the values match (both positive and negative peaks in the staircase wave), the output of the exclusive OR circuit EX forms a matching output logic "O". As a result, the selected grid of the vertical ROM is switched to the division ratio for the correction value.

By setting this correction value, the reference frequency signal φ (40
0KHz>, the standard time according to the division ratio at each step is taken as a unit time, and the correction time set for the peak step is added to the unit time multiplied by the number of steps until the peak value is reached. , so that a desired period can be obtained as a whole.

Although not particularly limited, by setting the unit time to be shorter than the desired cycle, the correction time at the peak step can be made longer than the unit time. This makes it possible to reduce the generation of harmonic components in analog signals.

[Effects] By switching the time in each step of the analog signal in the +11 staircase wave state into the reference time and the correction time, a tone signal with an arbitrary period can be formed by the combination thereof. This makes it possible to use a reference frequency signal with a relatively low frequency, thereby achieving the effect of reducing power consumption.

(2) Since the reference frequency can be made relatively low due to the above (1), the high speed required of the circuit can be relaxed.

This results in a relatively low electric power H? ! The effect is that it is possible to obtain a digital tone generating circuit whose operation can be fully guaranteed even under pressure.

(3) According to (11) above, since a relatively low reference frequency can be used, it is possible to construct the reference oscillation circuit using an inexpensive ceramic resonator.

(4) By providing a relatively long step for correction at the peak portion of the staircase wave, it is possible to reduce harmonic components of the output signal.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. For example, the step of switching the division ratio of the reference frequency signal to the division ratio for the correction value is not limited to the peak step in the stepped waveform, but may be provided at any step or across multiple steps. It may be. In addition, a circuit that forms a variable frequency-divided output of a reference frequency signal, and a specific circuit that forms a digital signal that changes into a staircase state from this frequency-divided output are as follows:
Various embodiments can be adopted.

[Application field]

The present invention can be widely used in various tone generating circuits that generate a plurality of types of tones (audio signals) from one reference frequency signal according to key inputs, in addition to digital tone generating circuits in pushbutton telephones.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining an example of its operation. C0NT...Counter circuit, G1...Nor gate circuit,
G2...Nant gate circuit, IVI-Iv4...Inverter circuit, Fl, F2...Flip flop circuit, EX
・・Exclusive OR circuit, IJ-CONT・・Jinson counter 1, D/A・・D/A conversion circuit

Claims (1)

[Claims] 1. A program counter circuit that counts reference frequency signals according to a key input signal, and a tone generation circuit that generates a step wave tone signal that changes according to pulses formed based on the output of the program counter circuit. and a correction circuit that switches the count value of the program counter to a correction value determined according to the frequency of the tone signal to be outputted at the specific staircase step. 2. The tone generation circuit includes a Johnson counter that receives a pulse signal formed according to the output of the program counter circuit, and a D/A conversion circuit that receives the output of the Johnson counter circuit, and detects the specific staircase step. 2. The digital tone generating circuit according to claim 1, wherein the circuit is an exclusive OR circuit receiving the least significant bit and most significant bit outputs of the Johnson counter circuit. 3. The program counter circuit is set by a vertical ROM in which the counted value and correction value are written, and the output of this ROM is selected by the key input. A digital tone generating circuit according to claim 1 or 2.