JPS6246492A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and is applicable to a semiconductor integrated circuit device having a built-in vertical ROM, such as a pushbutton type dual tone generation circuit. It is about effective techniques.

[Background technology]

Usually, storage MOS FETs are connected in series in the column direction.
The so-called vertical ROM (read-only memory) has a ratioless type (dynamic type) circuit system in which a precharged level is read out depending on whether or not it is discharged according to the stored information (for example, , see Japanese Patent Application Laid-Open No. 52-30388).

However, in a circuit device whose operation is extremely slow, such as a Pushbokun type dual tone generation circuit, the above ratioless type circuit system cannot be adopted. Therefore, the memory M connected in series with the load MOSFET
It is conceivable to use a ratio type (static type) circuit system that performs readout according to the conductance ratio with the OSFET. However, in this case, as a result of connecting a large number of storage MOS FETs in series, in order to achieve the desired large conductance for the load MOS FETs, in other words, it is necessary to ensure a margin for the input low level in the next stage circuit. Therefore, there is a problem in that it is necessary to make the size (conductance) of each storage MOSFET extremely large.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device incorporating a vertical ROM that performs static operation and occupies a small area.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by using a load MOS FET that performs constant current operation, static reading of the vertical ROM is performed.

〔Example〕

FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to a digital tone generating circuit. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques. This embodiment circuit generates four types of high-frequency tone signals for a pushbutton, although this is not particularly limited. In the following description, unless otherwise specified, MOS FET
is an N-channel MO5FET.

The reference frequency signal φ is configured by a reference frequency oscillation circuit (not shown). Although not particularly limited, this reference frequency oscillation circuit is configured by a ceramic oscillation circuit using a ceramic resonator, and generates a relatively low frequency signal, for example, 400 KHz.

This reference frequency signal φ is frequency-divided by the next program counter circuit C0NT. That is, each frequency division stage output 2 to 2 of the counter circuit C0NT receiving the reference frequency φ
32 is input to a vertical ROM which will be described next. In this vertical ROM, enhancement type MOSFETs are formed at the intersections of the grid, which are indicated by circles. Although not particularly limited, MOSFETs are not formed at other grid intersections.

MOSFETs to be connected in series, the MOSFETs
Two MOs adjacent to each other across a lattice point where no ET is formed
The source region and drain region of the SFET are connected by wiring made of, for example, aluminum.The ratio fluctuation that occurs when a depletion type MOSFET is formed at another lattice point can be avoided. The above MOSFETs are connected in series along the horizontal grid.The gates of the enhancement type MOSFETs connected in series with the horizontal grid are connected to a key operated by a key (button button). Signals 1 to 4 are supplied.The key human signals 1 to 4 are supplied to select two grids, respectively.One end of each MOSFET in series arranged in the grid is shared. The series MO5F is connected to the ground potential point of the circuit.
The other end of the ET is shared and used as an output. Although not particularly limited, there is a distance between this output point and the power supply voltage Vcc, but P
A channel type load MOS FETQ 1 is provided.

The conductance of this load MOS FETQ 1,
In order to increase the ratio of the conductance to the composite conductance of the series storage MOS FET,
A constant voltage V ref, which will be described later, is supplied between the gate and source of MOSFET QI.

Thereby, MOSFETQI operates as a constant power supply.

The output of the ROM is supplied to the input of the flip-flop circuit Fl via inverter circuits IV2 and IV3.

The flip-flop circuit F1 holds the output signal of the ROM in synchronization with the reference frequency signal φ by supplying the reference frequency signal φ to its clock terminal.

On the other hand, the key human signals 1 to 4 are Noah (N).

R) Supplied to the input of gate circuit G1. The output of this NOR gate circuit G1 is connected to the inverter circuit IV on the one hand.
It is supplied to one input of a NAND gate circuit G2 via I. The output Q of the flip-flop circuit F1 is supplied to the other input of the Nant gate circuit G2. The output of this Nant gate circuit G2 is supplied to the reset terminal of the counter circuit C0NT.

As a result, the counter circuit C0NT is controlled by the RO
It operates as a program counter according to the write information of M.

If none of the keys 1 to 4 are entered now,
All the signals are set to logic "0", which causes the output of gate circuit G1 to become logic "1", so that the output of inverter circuit I1 becomes logic "0". As a result, the output of the gate circuit G2 is set to logic "1", so the counter circuit C0NT remains in the reset state.
Its counting operation has been stopped.

When one of the key powers 1 to 4 is supplied, the output of the gate circuit G1 becomes logic "1", and one input of the gate circuit G2 becomes logic "1", and the output Set to logic 10”.

As a result, the counter circuit C0NT is released from the reset state and starts counting the reference frequency φ.

Enhancement type MO configured in series by the above-mentioned key input and the outputs 2 to 32 of the counter circuit C0NT
When all S FETs are turned on, their outputs are forced to logic "O'.

Therefore, the output Q of the flip-flop circuit F1 is changed from logic ""1" to logic "0", so the gate circuit G
2 becomes logic "1", and the counter circuit C0NT
to the reset state. Due to the reset state of the counter circuit C0NT, the output of the ROM is set to the logic '1', so the flip-flop circuit F1 becomes the logic @1' again in synchronization with the next clock φ, and the output of the counter circuit C0NT becomes the logic '1' again. Cancels the reset state. By repeating this process, a reference frequency signal φΦ divided output according to the frequency division ratio (count value) selected manually by the key is obtained from the output Q of the flip-flop circuit F1. by this,
Four types of variable frequency division output can be obtained according to the above-mentioned key input.

In order to form a stepped tone signal based on the pulse signal formed by such a frequency division operation, the output pulse of the flip-flop circuit F1 is frequency-divided by half by the flip-flop F2, and the pulse duty is is 5
It is converted into a pulse signal A of 0%. This pulse signal A is supplied to the Johnson counter circuit J-CONT.

The output of the NOR gate circuit G1 is supplied to the reset terminal of this Johnson counter circuit J-CONT.

As a result, when no key force is input, the operation of this counter circuit J-C0NT is stopped.

In this embodiment, two types of frequency division ratios are assigned to each of the keys 1 to 4.

Although not particularly limited, the above Johnson counter circuit J
- The least significant bit output and the most significant bit output of CON T are supplied to the exclusive OR circuit EX, and the peak value of the step-wave tone output signal OUT formed by the D/A conversion circuit D/I, which will be described later, is In the corresponding step, the frequency division ratio is switched. Therefore, the output of the exclusive OR circuit EX and the inverted signal formed by the inverter circuit IV4 are connected to one side of the grid (series MOSFET), two of which are provided for each of the keys 1 to 4. MO that selects complementary
SFET is arranged.

The outline of the operation of this embodiment circuit is as follows.

As described above, in response to one key input, a pulse A is generated according to the divided output of a preset reference frequency.

This pulse A causes the Johnson counter circuit J-CO to
NT forms a pulse signal delayed by every change (half cycle) of the pulse A.

As a result, in each half cycle, the bit increases by 1 bit starting from the least significant bit, and after reaching the peak value, it decreases, so the D/A converter circuit D/2 treats the half cycle of the pulse A as one step. Convert to a staircase wave analog signal.

The time of one step of the staircase wave is a fixed time that is an integral multiple (frequency division ratio) of the reference frequency φ. By setting this time according to the keys 1 to 4, it is possible to form analog signals OUT in a staircase wave state with different periods (frequencies).

In this case, if one type of frequency division ratio is used for each key manually, it becomes necessary to use a high reference frequency signal according to the least common multiple thereof. Therefore, in this embodiment, the step (
Positive in staircase wave.

(both negative peaks), the output of the exclusive OR circuit EX forms the logic "O" of the coincidence output. As a result, the selected grid of the vertical ROM is switched to the frequency division ratio for the correction value. By setting this correction value, using the reference frequency signal φ (400KHz), the reference time according to the frequency division ratio at each step is set as a unit time, and the unit time is multiplied by the number of steps until the peak value is reached. By adding the correction time provided to the peak step, the desired cycle (frequency) can be obtained as a whole.

FIG. 2 shows a circuit diagram of an embodiment of the vertical ROM.
1ROM consists of multiple memories MO5FETM connected in series.
One from I-M3. Column, composition. other.
The 1□ column is also composed of a plurality of storage MOSFETs connected in series. According to that memory information, this ;owttM
ooF E T ′t′qiqs10″”)71y/r
.

is provided as an enhancement type at a predetermined position.

Also, according to the memory information, enhancement
Parts where the single-channel MOS FET is not provided are connected in series by wiring.

The memory MO5FET at one end constituting each column above
The drain is on the output side and is commonly connected to the P-channel type load MOSFET QI. The sources of the MOS FETs at the other end of each column are connected to the ground point of the circuit. The above commonly connected memory MO5FET
One end (drain) is connected to the input terminal of the iter circuit IV2 that constitutes the sense amplifier. , a constant voltage Vref generated by the following voltage generating circuit is supplied.The P-channel MO5FETQ2 has its source connected to the power supply voltage terminal Vcc, and its gate and drain are connected in common, so that it is diode-connected. Similarly diode-connected P-channel MOSFETQ
3 is connected in series to the MOS FET Q 2. A diode-connected N-channel MOSFET Q4 similar to the above is connected in series to this MOS FET Q3.

Between the source side of this MOSFET Q4 and the ground potential point of the circuit, there is an N-channel MOSFET Q4 that operates as a resistance element by supplying a power supply voltage to its gate.
ETQ5 and resistance means R are connected in series. Although not particularly limited, a depression type P-channel MOSFET Q6 is provided, the gate of which is connected to the drain of the MOSFET Q5, and the drain of the MOSFET Q5 connected to the source of the MOSFET Q5. This MOSFET
The constant voltage Vref is generated from the source of Q6.

In this example, the threshold voltage V thn of N-channel MO5FET Q3 and P-channel MO3F
.

The sum of the threshold voltage v thp of ETQ4 (Vthn+
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'Phantom' iM OS FET Q 2 (
7) Threshold voltage vthp and Tig:
Voltage difference from threshold voltage V thpd of reflex type P-channel MO5FET Q6 vthp - vthp
a, yo, eh, engineering 7, 8. Ka, uh, 8□. 4th, 41 Based on the source voltage Vcc, the constant voltage Vref is calculated by the following formula (1
Represented by 1.

Vref = Vcc - ((Vthn + Vthp)
-(Vthρ-Vthpd) )... (1) Generally, in a CMO3 circuit, the P-channel O3FET and the channel MOSFET are 0 threshold.

Variations in low value voltage occur in a complementary manner, so...

□Vthn+71.2□, a. Yani 7, behind the scenes
□1, ,, A, 2. yo'-'-x, =g, t't,
a. Yo, 9 off, a: when. □, yo. 4
□Keyo 9, A47” L/y J run type MO5
FETQ6 and enhancement type M. 5FETQ2(7
) L, value voltage, y, phase, I 6. Fluctuation 1
Therefore, the differential voltage becomes constant. As a result, the constant voltage Vref is kept constant regardless of process variations, so the MOSFET Q1 performs constant current operation.

Since the impedance of the MOS FET Ql that performs the constant current operation becomes extremely large (the conductance becomes extremely small), a low level signal is obtained that is below the logic threshold voltage of the inverter circuit IV2 as a sense amplifier. Memory MOS F for
The conductance of ET, in other words, the element size can be made small.

Incidentally, according to the inventor's estimate, when using the constant current MOSFET QI, the area occupied by the memory MOSFET is smaller than when using a load MOSFET whose gate and drain are connected. Wow W'
A significant reduction of 1/2 can be achieved.

〔effect〕

(1) By using a load MOSFET that performs constant current operation as the load means of the vertical ROM, its conductance can be kept extremely small, so the storage MOSFET can be
Since the conductance of the ROM can also be reduced, the element size can be reduced, resulting in the effect that the area occupied by the vertical ROM that performs static operation can be significantly reduced.

(2) According to (11) above, the chip size of a semiconductor integrated circuit device incorporating a vertical ROM that performs static operation can be reduced in size, and a large number of semiconductor integrated circuits can be formed on one semiconductor wafer, allowing mass production. This has the effect of improving sexual performance.

(3) Due to (1) above, the power consumption of the vertical ROM can be kept constant regardless of the power supply voltage, making it suitable for semiconductor integrated circuit devices with a wide range of operating voltages, such as semiconductor integrated circuit devices for telephones. The effect is that it can be made into a In other words, it is possible to prevent an increase in current consumption as the power supply voltage increases.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, a vertical ROM may have an enhancement type MOSFET or a depression type MOSFET formed at its lattice points depending on the stored information. The constant voltage can be formed using various embodiments, such as one that uses the sum of the threshold voltages of a P-channel MOSFET and an N-channel MOSFET, or one that uses a silicon band gap. In addition, when a constant voltage is formed with the ground potential of the circuit as a reference, the constant current formed by that voltage is connected to the MO5FETQ1 in a current mirror configuration.
By supplying S FET, the MOSFET
The QI may be operated at a constant current.

In addition, the digital tone generator generates crystal heat according to the least common multiple of the number of steps constituting one period of the step-wave tone and a plurality of frequencies, for example, for color bursts used in color television receivers. Reference frequency signal (3,57954
5 MHz) and divide it to form tone signals of four different frequencies.

[Application field]

This invention is a digital tone generating circuit in a button telephone, and a vertical RO which performs static operation.
Various semiconductors including M (*can be widely used in integrated circuit devices).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a digital tone generating circuit to which the present invention is applied, and FIG. 2 is a circuit diagram showing an embodiment of a vertical ROM.

Claims (1)

[Claims] 1. A load MOSFET that performs constant current operation, and a series enhancement type M formed according to its stored information.
A semiconductor integrated circuit device characterized by including a vertical ROM made of OSFET. 2. The above load MOSFET is a P-channel MOSFET.
2. The semiconductor integrated circuit device according to claim 1, wherein the series MOSFET is an N-channel MOSFET. 3. The semiconductor integrated circuit device constitutes a digital tone generation circuit, and the vertical ROM decodes an input digital signal to set a frequency division ratio of a reference frequency signal. A semiconductor integrated circuit device according to claim 1 or 2.