JPH0787474B2 - Digital tone generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital tone generating circuit and, for example, to a technique effectively used for a push button type dual tone telephone.

[Background technology]

Conventionally, a digital tone generator used in a push button type dual tone telephone is known (for example, 197 from AMI (AMERICAN MICRO SYSTEMS INC)).
Refer to the product catalog issued in January 1997, pages 4 to 14 of the digital tone generator "S2559A / B / C / D").

The conventional digital tone generator forms a plurality of desired tones (frequency signals 697 Hz to 1633 Hz) with high precision, that is, defines a tone period to be generated with high precision. A reference frequency signal (3.579545 MHz), which is formed by a crystal oscillation circuit for color burst used in, for example, a color television receiver, is used according to the least common multiple of the number of steps and these frequencies. Since such a high reference frequency signal is used, it becomes a cause of hindering low power consumption and low operating voltage.

[Object of the Invention]

It is an object of the present invention to provide a digital tone generating circuit which has low power consumption and low operating voltage.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the count value of the program counter circuit that counts the reference frequency signal according to the key input signal is switched to the correction value at a specific step step or step wave step of the staircase tone signal to be formed, so that the desired frequency is obtained. It forms a staircase tone signal.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a digital tone generating circuit according to the present invention. Although not particularly limited, each circuit block shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Although not particularly limited, this embodiment circuit forms four types of tone signals on the common row side for push buttons.

The reference frequency signal φ is composed of a reference frequency oscillation circuit (not shown). The reference frequency oscillation circuit is not particularly limited, but is configured by a ceramic oscillation circuit using a ceramic oscillator, and has a relatively low frequency signal such as 400 KHz.

This reference frequency signal φ is output to the next program counter circuit.
Divided by CONT. That is, the reference frequency φ
Each division stage output 2 to 32 of the counter circuit CONT that receives
Input to M (Read Only Memory). The frequency dividing stage output 2 of the counter circuit CONT outputs the reference frequency signal φ of 2
The frequency-divided output, frequency-division stage output 4 is the frequency-divided reference frequency signal φ divided by 4, frequency-division stage output 8 is the frequency-divided reference frequency signal φ divided by 8, and frequency-division stage output 16 is the frequency-divided stage output φ. The output divided by 16 and the division stage output 32 are outputs obtained by dividing the reference frequency signal φ by 32. This ROM is a vertical mask in which enhancement type MOSFETs are formed at the points indicated by ○ at the grid-like intersections.
Composed of ROM. Although not shown, a depression type MOSFET is formed at the intersection of the other lattices. The MOSFETs are connected in series along a horizontal grid. Enhancement-type MOSF in series with this horizontal grid
Key input signals 1 to 4 formed by a key (push button) are supplied to the gate of the ET. The key input signals 1 to 4 are supplied so as to select two grids, respectively. Series-shaped MOSFETs arranged in a grid pattern
Has one end connected in common and connected to the ground potential point of the circuit. Further, the other end of the series MOSFET is commonly used as an output. Between the output point and the power supply voltage Vcc, although not particularly limited, a load MOSFET Q1 which is operated by the bias voltage Vref is provided. The output of the above ROM is
Flip-flop circuit F through inverter circuits IV2 and IV3
Supplied on one input. This flip-flop circuit F1
Is supplied to the clock terminal in synchronization with the reference frequency signal φ,
Holds the output signal of ROM.

On the other hand, the key input signals 1 to 4 are supplied to the input of the NOR gate circuit G1. The output of the NOR gate circuit G1 is supplied to one input of a NAND gate circuit G2 via the inverter circuit IV1 on the one hand. The output Q of the flip-flop circuit F1 is supplied to the other input of the NAND gate circuit G2. The output of the NAND gate circuit G2 is supplied to the reset terminal of the counter circuit CONT.

As a result, the counter circuit CONT operates as a program counter according to the write information of the ROM.

Now, if none of the key inputs 1 to 4 are input,
All signals are set to logic "0". This allows the gate circuit
Since the output of G1 becomes logic "1", the output of the inverter circuit IV1 becomes logic "0". This allows the gate circuit G2
Since the output of the counter circuit is set to logic "1", the counter circuit CO
NT remains in the reset state and stops its counting operation. At this time, since the frequency division output stages 2, 4, 8, 16, 32 of the counter circuit CONT are all set to logic "0", the output Q of the flip-flop circuit F1 is set to logic "1". There is.

When one of the key inputs 1 to 4 is supplied, the output of the gate circuit G1 becomes logical "0", and one input of the gate circuit G2 becomes logical "1" and its output Is set to logic "0". As a result, the counter circuit CONT becomes
The reset state is released, and the counting operation of the reference frequency φ is started from T0 in FIG. FIG. 3 is a timing chart showing an example of the frequency dividing operation when the key input 1 is selected by setting it to logical "1". Immediately after the counting operation of the reference frequency signal φ is started as will be described later, the output of the exclusive OR circuit EX described later is set to the logic “1”. Therefore, when all the enhancement-type MOSFETs in the serial form are turned on by the key input, the outputs 2 to 32 of the counter circuit CONT, and the output of the exclusive OR circuit EX described later, the output is a logic "0". "I will. That is, the third
According to the example in the figure, the frequency division output stage 2 (division by 2) and the frequency division output stage
The output of ROM is inverted to logic "0" in synchronization with time T1 when both 16 (division by 16) outputs are set to logic "1". Therefore, the output Q of the flip-flop circuit F1 is synchronized with the reference frequency signal φ at the time T2 in FIG. 3 from the logic “1” to the logic “0”.
The output of the gate circuit G2 is logic "1" in synchronization with this.
Then, the counter circuit CONT is reset. By resetting the counter circuit CONT, all of the frequency division stage outputs 2, 4, 8, 16, 32 of the count circuit CONT are set to logic "0", whereby the output of the ROM is set to logic "1". Therefore, the flip-flop circuit F1 becomes the logic "1" again in synchronization with the timing when the reference clock signal φ is changed from the logic "1" to the logic "0", that is, the time T3 in FIG. When the output of the flip-flop circuit F1 is set to logic "1", the output of the gate circuit G2 is inverted to logic 0 in synchronization with this, and the reset state of the counter circuit CONT is released. By repeating this, from the output Q of the flip-flop circuit F1, the divided output of the reference frequency signal φ according to the dividing ratio (count value) selected by the key input is obtained. According to FIG. 3, the operation shown from time T0 to T3 is repeated, and the flip-flop circuit F1 starts the third operation.
The output waveform indicated by F1 (Q) in the figure is repeatedly obtained.
In this way, one of the four variable frequency division outputs according to the key input is obtained. In the description so far, it is assumed that the output of the exclusive OR circuit EX, which will be described later, is set to the logic "1", for example.

Since the stepped tone signal is formed based on the pulse signal formed by the frequency dividing operation, the output pulse of the flip-flop circuit F1 is
It is divided by 1/2 by F2 and converted into a pulse signal A with a pulse duty of 50%. For example, in a well-known toggle type flip-flop circuit of the flip circuit F2, the state of the output Q is applied every time a clock pulse is applied to the clock terminal C when the reference frequency signal φ supplied thereto is logic "1". Are to be reversed. Although not particularly limited, the flip-flop circuit F2 in FIG.
The output Q of the flip-flop circuit F1 is applied to the clock terminal C.
In response to this, the state of the output is inverted internally in synchronization with the clock pulse of the inverted signal. FIG. 3 shows an example of the state by the waveforms ▲ ▼ and F2 (Q), and the output of the flip-flop circuit F2 is inverted in synchronization with the time T3. The pulse signal A is supplied to the Johnson counter circuit J-CONT. The output of the NOR gate circuit G1 is supplied to the reset terminal of the Johnson counter circuit J-CONT. As a result, when no key input is input, this counter circuit J-CO
NT has its operations stopped. Here, the Johnson counter J-CONT is not particularly limited, but it can be configured by connecting the inverted output of the final stage flip-flop of the shift register to the input of the first stage flip-flop, and the normal output of each flip-flop is connected in parallel. Output. All bits of this parallel output are logical "0" in the reset state.
Are sequentially set to logic "1" from the lower bits, and after all bits are set to logic "1", the bits are sequentially changed to "0" from the lower bits. The parallel output of multiple bits of this Johnson counter J-CONT is supplied to the D / A conversion circuit D / A and
A tone signal having a waveform similar to a sine curve which is A-converted and is stepwise changed according to the output change of the Johnson counter J-CONT is formed.

In this embodiment, two types of frequency division ratios are assigned to the respective key inputs 1 to 4. Although not particularly limited, the exclusive OR circuit EX is used for the least significant bit output B and the most significant bit output C of the Johnson counter circuit J-CONT.
And the frequency division ratio is switched in the step corresponding to the peak value of the staircase tone output signal OUT formed by the D / A conversion circuit D / A. Therefore, the output of the exclusive OR circuit EX,
The inverted signal formed by the inverter circuit IV4 is
For selecting one of two grids (series MOSFETs) provided for each of the key inputs 1 to 4 in a complementary manner
Supplied to the gate of the MOSFET. That is, the peak (positive polarity and negative polarity) of the tone signal waveform is the Johnson counter J-
It is formed in response to the output of all bit logic "1" and the output of all bit logic "0" of CONT. The exclusive OR circuit EX detects the timing based on the least significant bit output B and the most significant bit output C, inverts the output to logic "0" only during that period, and receives the output of the inverter IV4 in the ROM. MO
A series route including SFET can be selected. On the other hand, in the ROM, the output of the exclusive OR circuit EX is directly received.
ET takes the cut-off state.

The tone generating operation of this embodiment circuit will be described with reference to the waveform diagram of FIG.

As described above, for one key input, the pulse A is formed according to the divided output of the preset reference frequency.
By this pulse A, Johnson counter circuit J-CONT
Forms a pulse signal delayed by a half cycle for each change of the pulse A, like outputs B to C. As a result, in the half cycle, the least significant bit increases by 1 bit at a time, and after it reaches the peak value, it decreases. Therefore, the D / A conversion circuit D
/ A converts the half cycle of the pulse A into a step-wave analog signal having one step.

The time of one step of the staircase wave is a fixed time that is an integral multiple (frequency division ratio) of the reference frequency φ. By setting this time according to the key inputs 1 to 4, it is possible to form the analog signal OUT in the staircase state having different cycles (frequency). At this time, if one type of frequency division ratio is used for each key input as in the prior art, a plurality of types of tone frequencies to be formed in response to the key input have a high standard according to the least common multiple thereof. It will be necessary to use frequency signals. On the other hand, in this embodiment, the exclusive OR is executed at the step (both positive and negative peaks in the staircase wave) where the least significant bit output B and the most significant bit signal C of the Johnson counter circuit J-CONT match. The output of the circuit EX forms the logic "0" of the coincidence output. As a result, the selected grid of the vertical ROM is switched to the division ratio for the correction value. By setting this correction value, using the above-mentioned reference frequency signal φ (400 KHz), the steps until the peak value is reached with the reference time according to the division ratio in each step excluding the peak value of the staircase wave as the unit time In the time multiplied by several times,
By adding the corrected time allotted to the peak step, the desired period is obtained as a whole.

Although not particularly limited, the correction time at the peak step is set to be longer than the unit time by setting the unit time shorter than the desired period. This makes it possible to reduce the generation of harmonic components of the analog signal.

[Effect]

(1) By switching the time of each step of the analog signal in the stepped wave state to the reference time and the correction time, it is possible to form a tone signal of an arbitrary cycle by the combination thereof. In other words, the connection time of the step wave step at the predetermined phase of the step tone signal waveform is not used for a plurality of types of tone frequencies to be formed according to the key input signal, without using a signal with a high frequency according to the least common multiple thereof. Is changed, and the half time for the period corresponding to the desired tone frequency can be absorbed or adjusted by the changed time. As a result, a reference frequency signal having a relatively low frequency can be used, so that an effect of achieving low power consumption can be obtained.

(2) Since the reference frequency can be made relatively low by the above (1), the high speed required for the circuit can be relaxed. As a result, it is possible to obtain the effect that a digital tone generating circuit that can sufficiently guarantee its operation even with a relatively low power supply voltage can be obtained.

(3) According to the above (1), since a comparatively low reference frequency can be used, an effect that the reference oscillation circuit can be configured by using an inexpensive ceramic vibrator is obtained.

(4) By providing a relatively long step for correction in the peak portion of the staircase wave, it is possible to obtain the effect that the harmonic component of the output signal can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, the step of switching the frequency division ratio of the reference frequency signal to the frequency division ratio for the correction value is not limited to the peak step in the stepped waveform, and is provided over any step or a plurality of steps. Good. Further, a circuit that forms a variable frequency division output of the reference frequency signal, and a specific circuit that forms a digital signal that changes from this frequency division output to a staircase
Various embodiments can be adopted.

[Field of application]

INDUSTRIAL APPLICABILITY The present invention can be widely used in various tone generating circuits for forming a plurality of types of tones (voice signals) from one reference frequency signal according to a key input, as well as a digital tone generating circuit in a push button telephone.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining an example of this operation. FIG. 3 is a timing chart of an example of the operation of dividing the reference frequency signal. CONT …… counter circuit, G1 …… NOR gate circuit, G2 ……
NAND gate circuit, IV1-IV4 ... Inverter circuit, F1, F
2 ... Flip-flop circuit, EX ... Exclusive OR circuit, IJ-CONT ... Johnson counter circuit, D / A ... D / A
Conversion circuit

Claims (4)

[Claims] 1. A program counter circuit that changes its output each time the reference frequency signal is counted by the number of cycles based on an instruction of a key input signal, and a staircase that sequentially changes in synchronization with the output change of the program counter circuit. Tone control circuit for generating a wavy tone signal and for switching control of the number of cycles of the reference frequency signal to be counted by the program counter circuit for a predetermined period by detecting a predetermined step wave step in the tone signal to be generated A digital tone generating circuit, characterized in that it comprises: 2. The tone generation circuit includes a Johnson counter that performs a counting operation in synchronization with an output change of the program counter circuit, and a D / A conversion circuit that receives the output of the Johnson counter. 2. A digital circuit according to claim 1, further comprising a logic circuit for detecting a match between the least significant bit output and the most significant bit output of the Johnson counter in order to detect the predetermined staircase wave step. Tone generation circuit. 3. The program counter circuit divides the reference frequency signal, a plurality of frequency division outputs having different frequency division ratios and outputted in parallel from the frequency division circuit, and the key. A vertical ROM in which stored information is selected based on an input signal, and the timing of output change of the program counter circuit is variable according to the selected state of the stored information. The digital tone generation circuit described in the item. 4. The correction circuit includes a transistor, which is complementarily switch-controlled by receiving an output of the logic circuit for detecting the coincidence and an inverted output thereof, arranged in the vertical ROM. A digital tone generating circuit according to claim 3.