JPS603772B2 - Manufacturing method for semiconductor devices - Google Patents
Manufacturing method for semiconductor devicesInfo
- Publication number
- JPS603772B2 JPS603772B2 JP54103052A JP10305279A JPS603772B2 JP S603772 B2 JPS603772 B2 JP S603772B2 JP 54103052 A JP54103052 A JP 54103052A JP 10305279 A JP10305279 A JP 10305279A JP S603772 B2 JPS603772 B2 JP S603772B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- impurity
- semiconductor substrate
- insulating coating
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 60
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000010410 layer Substances 0.000 claims description 86
- 239000012535 impurity Substances 0.000 claims description 46
- 239000000758 substrate Substances 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 239000011247 coating layer Substances 0.000 claims description 18
- 229910052709 silver Inorganic materials 0.000 claims description 14
- 239000004332 silver Substances 0.000 claims description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 8
- 229910052711 selenium Inorganic materials 0.000 claims description 8
- 239000011669 selenium Substances 0.000 claims description 8
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000012670 alkaline solution Substances 0.000 description 2
- 150000004770 chalcogenides Chemical class 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- -1 silver ions Chemical class 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 125000003748 selenium group Chemical group *[Se]* 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は、半導体基体内にその主面側より所要の導電型
を有する不純物の拡散されてなる半導体領域が形成され
、又半導体基体の主面上にこれと絶縁されて半導体基体
内に形成された半導体領域に連結して延長せる導電性層
が形成されてなる構成を有する半導体装置の製法に関し
、特に半導体領域を少ない工程数で高精密に得ることが
出来、且導電性層の半導体基体の主面上にこれと絶縁し
て延長せる構成を簡易に得ることが出来る新規な斯種半
導体装置の製法を提案せんとするものである。DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a semiconductor region is formed by diffusing an impurity having a desired conductivity type from the main surface side of the semiconductor substrate, and is insulated from the main surface of the semiconductor substrate. The present invention relates to a method for manufacturing a semiconductor device having a structure in which a conductive layer is formed to connect and extend a semiconductor region formed in a semiconductor substrate, and in particular, the semiconductor region can be obtained with high precision in a small number of steps, and The purpose of this invention is to propose a novel method for manufacturing such a semiconductor device, which can easily provide a structure in which a conductive layer extends on the main surface of a semiconductor substrate while being insulated therefrom.
本願発明者などは、セレンを主成分とする第1の層(非
晶質カリコゲナィド層)と、銀又は銀を含む第2の層と
よりなる無機フオトレジスト材層がフオトレジストとし
ての高解像特性を有すること、このような高解像特性を
有する無機フオトレジスト材層に、所要の導電型を与え
る不純物を比較的多量含有させても、フオトレジストと
しての高解像特性が損なわれないこと、従って、その不
純物を含有している無機フオトレジスト材層を「半導体
基体上で、パターン化し、その不純物を含有しているパ
ターン化された無機フオトレジスト材層を不純物含有層
として、その不純物含有層から、不純物を半導体基体内
に熱拡散させれば、半導体基体上に別途不純物拡散用層
を形成して、これから半導体基体内に不純物を熱拡散さ
せる必要ないこ、半導体基体内に、所要の導電型を有す
る半導体領域を、高精度に形成することができること、
この不純物の熱拡散を、不純物含有層が、耐熱性絶縁被
覆層によって覆われている状態で、なせば、不純物含有
層を構成している無機フオトレジスト材層を不必要に昇
華乃至蒸発させることないこ、効果的に不純物を半導体
基体内に熱拡散させることができること、このような効
果をもたらす耐熱性絶縁被覆層を、その上に半導体基体
内に形成された半導体領域に連結している導電性層を半
導体基体と絶縁して延長させ得る、層にさせることがで
きることなどを発見乃至確認した。The present inventors have discovered that an inorganic photoresist material layer consisting of a first layer containing selenium as a main component (amorphous chalcogenide layer) and a second layer containing silver or silver has high resolution as a photoresist. Even if an inorganic photoresist material layer having such high-resolution characteristics contains a relatively large amount of impurities that impart a desired conductivity type, the high-resolution characteristics as a photoresist will not be impaired. Therefore, the inorganic photoresist material layer containing the impurity is patterned on the semiconductor substrate, and the patterned inorganic photoresist material layer containing the impurity is used as the impurity-containing layer. If the impurities are thermally diffused from the layer into the semiconductor substrate, there is no need to form a separate impurity diffusion layer on the semiconductor substrate and then thermally diffuse the impurities into the semiconductor substrate. A semiconductor region having a conductivity type can be formed with high precision;
If this thermal diffusion of impurities is performed while the impurity-containing layer is covered with a heat-resistant insulating coating layer, the inorganic photoresist material layer constituting the impurity-containing layer may be unnecessarily sublimated or evaporated. The reason is that impurities can be effectively thermally diffused into the semiconductor substrate, and a heat-resistant insulating coating layer that brings about this effect can be coated with a conductive layer connected to the semiconductor region formed within the semiconductor substrate. It was discovered or confirmed that the magnetic layer can be extended and formed into a layer while insulating it from the semiconductor substrate.
本発明は、このような発見乃至確認に基き提案されたも
のである。以下図面を伴なつて本発明の一例を述べるに
、第1図に示す如き例えばN型の半導体基体1が予め用
意され、而してその主面2上に第2図に示す如く例えば
P型不純物を含むセレンを主成分とせる層3とその層3
上に形成された銀又は銀を含む層4とよりなる無機フオ
トレジスト材層5を形成する。The present invention was proposed based on such discovery or confirmation. An example of the present invention will be described below with reference to the drawings. For example, an N-type semiconductor substrate 1 as shown in FIG. 1 is prepared in advance, and a P-type semiconductor substrate 1 as shown in FIG. Layer 3 whose main component is selenium containing impurities and its layer 3
An inorganic photoresist material layer 5 consisting of silver or a layer 4 containing silver formed thereon is formed.
実際上斯る無機フオトレジスト材層5は、基体1の主面
上に、層3を真空蒸着又はスパッタリングによりセレン
を主成分とするもセレンとゲルマニウムとを主成分とせ
る、望ましくはSe7o蛇3oの組成乃至その近傍の組
成を有する非晶質カルコゲナィド層として形成し、次に
層3上に層4を真空蒸着又はスパッタリング若しくは層
3の銀イオンを含む溶液への浸積により銀層、銀のカル
コゲナィド層、銀のハラィド層等として形成することに
よって得られる。In fact, such an inorganic photoresist material layer 5 is formed on the main surface of the substrate 1 by vacuum evaporation or sputtering to form a layer 3 containing selenium as a main component, preferably selenium and germanium as main components. A layer 4 is formed on the layer 3 by vacuum evaporation or sputtering, or by immersing the layer 3 in a solution containing silver ions. It can be obtained by forming a chalcogenide layer, a silver halide layer, or the like.
次に第3図に示す如く無機フオトレジスト材層5に対し
てその層4側より符号6で示す如く光、電子線、イオン
線等による所要のパターンの露光をなさしめ、層3及び
4の露光された領域を層3の露光されざる領域3aに比
しアルカリ溶液でなる現像液に対して高い不落藤性を有
する領域7として得、続いてアルカリ溶液でなる現像液
を用いた現像処理をなして第4図に示す如く領域7は残
すも層3及び4の露光されざる領域3a及び4bを基体
1上より除去し、斯くて領域7を露光のパターンに応じ
たパターンを有するフオトレジスト材層5によるP型不
純物を含有せる不純物含有層として得る。Next, as shown in FIG. 3, the inorganic photoresist material layer 5 is exposed to light, electron beam, ion beam, etc. in a desired pattern from the layer 4 side as shown by the reference numeral 6, and the layers 3 and 4 are exposed. The exposed area is obtained as a region 7 having a higher resistance to a developer made of an alkaline solution than the unexposed region 3a of the layer 3, and then developed using a developer made of an alkaline solution. As shown in FIG. 4, the unexposed regions 3a and 4b of layers 3 and 4 are removed from the substrate 1, leaving the region 7, and thus the region 7 is covered with a photoresist material having a pattern corresponding to the exposure pattern. The layer 5 is obtained as an impurity-containing layer containing P-type impurities.
次に基体1上に第5図に示す如く領域7従って不純物含
有層を覆って例えばSi02、Si3N4等の絶縁材で
なる耐熱性絶縁被覆層8をそれ自体は公知の種々の方法
によって形成する。Next, as shown in FIG. 5, a heat-resistant insulating coating layer 8 made of an insulating material such as Si02 or Si3N4 is formed on the substrate 1, covering the region 7 and therefore the impurity-containing layer, by various methods known per se.
次に熱処理をなし基体1の不純物含有層7下の領域に第
6図に示す如く不純物含有層7よりのP型不純物の熱拡
散されてなるP型半導体領域9を形成する。Next, heat treatment is performed to form a P-type semiconductor region 9 in the region below the impurity-containing layer 7 of the substrate 1 by thermally diffusing the P-type impurity from the impurity-containing layer 7, as shown in FIG.
この場合熱処理により、絶縁被覆層8の材質によっては
不純物含有層7を構成せる材料が絶縁被覆層8内に全て
溶け込むか一部溶け込み不純物含有層7が全くなくなる
か図示の如く僅かしか残らないものとなるものである。
次に耐熱性絶縁被覆層8の半導体領域9に対応する位置
にそれ自体は公知の手段を用いて半導体領域9を外部に
臨ませる為の窓10を形成し、又不純物含有層7が図示
の如く半導体領域9上に残っているとすれば熱処理、エ
ッチング処理等によって第8図に示す如くこれを半導体
領域9上より除去し、結局半導体領域9を窓10を通じ
て外部に臨ませる様にし、続いて絶縁被覆層8上に第9
図に示す如くそれ自体は公知の手段によって窓10を通
じて半導体領域に連結して延長せる例えば配線層となる
導電性層11を形成し、斯くてN型の半導体基体1内に
その王面2側よりP型不純物の拡散されてなる半導体領
域9が形成され、且半導体基体1の主面2上にこれと絶
縁被覆層8にて絶縁されて半導体領域9に連結して延長
せる導電性層11が形成されてなる構成を有する半導体
装置を得る。In this case, due to the heat treatment, depending on the material of the insulating coating layer 8, the material constituting the impurity-containing layer 7 may completely or partially dissolve into the insulating coating layer 8, and the impurity-containing layer 7 may disappear completely or only a small amount remains as shown in the figure. This is the result.
Next, a window 10 for exposing the semiconductor region 9 to the outside is formed at a position corresponding to the semiconductor region 9 of the heat-resistant insulating coating layer 8 using a method known per se, and the impurity-containing layer 7 is If it remains on the semiconductor region 9 as shown in FIG. 8, it is removed from the semiconductor region 9 by heat treatment, etching treatment, etc. as shown in FIG. A ninth layer is formed on the insulating coating layer 8.
As shown in the figure, a conductive layer 11, for example, a wiring layer, which can be connected and extended to the semiconductor region through a window 10, is formed by means known per se, and is thus formed in an N-type semiconductor substrate 1 on its crown surface 2. A semiconductor region 9 in which P-type impurities are diffused is formed, and a conductive layer 11 is formed on the main surface 2 of the semiconductor substrate 1, insulated from this by an insulating coating layer 8, and connected and extended to the semiconductor region 9. A semiconductor device having a configuration in which is formed is obtained.
以上にて本発明の一例が明らかとなったが、本発明によ
れば、半導体基体1の主面2上に、所要の導電型を与え
る不純物を含むセレンを主成分とせる層3とその層3上
に形成された銀又は銀を含む層4とよりなる無機フオト
レジスト材層5を形成し、次にその無機フオトレジスト
材層5に対する所要のパターンの露光、続く現像処理に
より無機フオトレジスト材層5による露光のパターンに
応じたパターンを有する不純物含有層7を形成し、次に
上記半導体基体1の主面2上に不純物含有層7を覆って
耐熱性絶縁被覆層8を形成し、次に熱処理をなすという
ことで、半導体基体1の不純物含有層7下の領域に不純
物含有層7よりの不純物の拡散されてなる半導体領域9
を形成することが出来、従って半導体領域9を簡単な少
ない工程を以つて得ることが出来、しかもその半導体領
域9は、基体1上に形成された無機フオトレジスト材層
6に対する露光、続く現像処理をなして得られる不純物
含有層7を半導体領域9を得る為の不純物源として得ら
れるので、無機フオトレジスト材層5に対する露光のパ
ターンに応じたパターンを以つて高精度に得ることが出
釆、又不純物含有層7を不純物源として半導体基体1内
に半導体領域9を形成する場合、絶縁被覆層8を有する
ので、不純物含有層7を不必要に昇華乃至蒸発させるこ
とないこ、且つ不純物含有層7に含まれる不純物が不必
要に外部に拡散されることないこ効果的に基体1側に拡
散し、依って半導体領域9を所期の不純物濃度を有する
ものとして容易に得ることが出釆、更に無機フオトレジ
スト材層5がセレンを主成分とせる層3とその上に形成
された銭又は銀を含む層4とよりなることにより、高感
度で高精度を以つて不純物含有層7を得ることが出来、
従って半導体領域9を高精度で得ることが出来る等の大
なる特徴を有するものである。An example of the present invention has been clarified above, and according to the present invention, on the main surface 2 of the semiconductor substrate 1, a layer 3 mainly composed of selenium containing an impurity imparting a desired conductivity type, An inorganic photoresist material layer 5 consisting of silver or silver-containing layer 4 formed on 3 is formed, and then the inorganic photoresist material layer 5 is exposed to light in a desired pattern, followed by development treatment to form an inorganic photoresist material. An impurity-containing layer 7 having a pattern corresponding to the exposure pattern of the layer 5 is formed, and then a heat-resistant insulating coating layer 8 is formed on the main surface 2 of the semiconductor substrate 1 to cover the impurity-containing layer 7. As a result, a semiconductor region 9 is formed in which impurities from the impurity-containing layer 7 are diffused into a region under the impurity-containing layer 7 of the semiconductor substrate 1.
Therefore, the semiconductor region 9 can be obtained with a simple and small number of steps, and the semiconductor region 9 can be formed by exposing the inorganic photoresist material layer 6 formed on the substrate 1 to light, followed by a development treatment. Since the impurity-containing layer 7 obtained by the above method can be used as an impurity source for obtaining the semiconductor region 9, it is possible to obtain a pattern with high precision according to the exposure pattern for the inorganic photoresist material layer 5. Furthermore, when forming the semiconductor region 9 in the semiconductor substrate 1 using the impurity-containing layer 7 as an impurity source, since the insulating coating layer 8 is provided, the impurity-containing layer 7 can be prevented from being sublimated or evaporated unnecessarily. The impurities contained in 7 are effectively diffused to the substrate 1 side without being unnecessarily diffused to the outside, and therefore it is possible to easily obtain the semiconductor region 9 having the desired impurity concentration. Further, since the inorganic photoresist material layer 5 is composed of the layer 3 containing selenium as a main component and the layer 4 containing silver or silver formed thereon, an impurity-containing layer 7 is obtained with high sensitivity and high precision. I can do it,
Therefore, it has great features such as being able to obtain the semiconductor region 9 with high precision.
又半導体領域9を上述せる特徴を有して得て后耐熱性絶
縁被覆層8に窓10を穿設し、次に絶縁被覆層8上に延
長せる導電性層を形成する工程をとるということで、半
導体基体1の主面2上にこれと絶縁されて半導体領域9
に連結して延長せる導電性層1 1を形成することが出
来るので、その導電性層11を容易に得ることが出来、
しかも導電性層11の半導体基体1の主面2上にこれと
絶縁して延長せる構成が、熱処理により半導体領域9を
形成する場合に不純物含有層7に含む不純物が不必要に
外部に拡散せしめる為にも適用されている絶縁被覆層8
を適用して得られているので、その構成を簡易に得るこ
とが出来る等の大なる特徴を有するものである。Further, after obtaining the semiconductor region 9 with the above-mentioned characteristics, a step is taken to form a window 10 in the heat-resistant insulating coating layer 8 and then forming a conductive layer extending over the insulating coating layer 8. A semiconductor region 9 is formed on the main surface 2 of the semiconductor substrate 1 and is insulated therefrom.
Since it is possible to form a conductive layer 11 that can be connected and extended to the conductive layer 11, the conductive layer 11 can be easily obtained.
Moreover, the structure in which the conductive layer 11 extends over the main surface 2 of the semiconductor substrate 1 in an insulated manner causes impurities contained in the impurity-containing layer 7 to unnecessarily diffuse to the outside when the semiconductor region 9 is formed by heat treatment. Insulating coating layer 8 which is also applied for
Since it is obtained by applying the above, it has great features such as being able to easily obtain the configuration.
尚上述に於ては本発明の一例を示したに留まり、上述せ
る「N型」を「P型」と読替えることも出来、又半導体
領域を半導体基体と同じ導電型に形成する様になすこと
も出来、又無機フオトレジスト材層に対する現像処理を
プラズマエッチング処理とすることも出釆、その他本発
明の精神を脱することないこ種々の変型変更をなし得る
であろう。The above description merely shows an example of the present invention, and the above-mentioned "N type" can also be read as "P type", and the semiconductor region may be formed to have the same conductivity type as the semiconductor substrate. It is also possible to use plasma etching as the development treatment for the inorganic photoresist material layer, and various other modifications may be made without departing from the spirit of the present invention.
第1図〜第9図は本発明に依る半導体装置の製法の一例
を示す順次の工程に於ける略線的断面図である。
図中1は半導体基体、2は主面、3はセレンを主成分と
せる層、4は銀又は銀を含む層、5は無機フオトレジス
ト材層、7は領域、8は耐熱性絶縁被覆層、9は半導体
領域、10は窓、11は導電性層を夫々示す。
第1図
第2図
第3図
第4図
第5図
第6図
第7図
第8図
第9図FIGS. 1 to 9 are schematic cross-sectional views in successive steps showing an example of a method for manufacturing a semiconductor device according to the present invention. In the figure, 1 is a semiconductor substrate, 2 is a main surface, 3 is a layer mainly composed of selenium, 4 is a layer containing silver or silver, 5 is an inorganic photoresist material layer, 7 is a region, and 8 is a heat-resistant insulating coating layer. , 9 is a semiconductor region, 10 is a window, and 11 is a conductive layer. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9
Claims (1)
物を含むセレンを主成分とせる第1の層と、該第1の層
上に形成された銀又は銀を含む第2の層とよりなる無機
フオトレジスト材層を形成する工程と、 上記無機フオ
トレジスト材層に対する所要のパターンの露光、続く現
像処理により、上記無機フオトレジスト材層による、上
記露光のパターンに応じたパターンを有する不純物含有
層を形成する工程と、 上記半導体基体の主面上に、上
記不純物含有層を覆って、耐熱性絶縁被覆層を形成する
工程と、 上記不純物含有層を上記耐熱性絶縁被覆層で
覆っている状態での熱処理により、上記半導体基体の上
記不純物含有層下の領域に、上記不純物含有層よりの不
純物の拡散されてなる半導体領域を形成する工程と、
上記耐熱性絶縁被覆層に上記半導体領域を外部に臨ませ
る窓を形成する工程と、 上記耐熱性絶縁被覆層上に上
記窓を通じて上記半導体領域に連結して延長せる導電性
層を形成する工程とを含む事を特徴とする半導体装置の
製法。1. On the main surface of the semiconductor substrate, a first layer mainly composed of selenium containing impurities that imparts a desired conductivity type, and a second layer containing silver or silver formed on the first layer. A process of forming an inorganic photoresist material layer, exposing the inorganic photoresist material layer in a desired pattern, and a subsequent development treatment, thereby removing impurities from the inorganic photoresist material layer having a pattern corresponding to the exposure pattern. forming a heat-resistant insulating coating layer on the main surface of the semiconductor substrate, covering the impurity-containing layer; and covering the impurity-containing layer with the heat-resistant insulating coating layer. forming a semiconductor region in which impurities from the impurity-containing layer are diffused in a region of the semiconductor substrate under the impurity-containing layer by heat treatment in a state where
forming a window in the heat-resistant insulating coating layer that allows the semiconductor region to be exposed to the outside; forming a conductive layer on the heat-resistant insulating coating layer that connects and extends to the semiconductor region through the window; A method for manufacturing a semiconductor device characterized by comprising:
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54103052A JPS603772B2 (en) | 1979-08-13 | 1979-08-13 | Manufacturing method for semiconductor devices |
US06/174,275 US4350541A (en) | 1979-08-13 | 1980-07-31 | Doping from a photoresist layer |
FR8017774A FR2463509B1 (en) | 1979-08-13 | 1980-08-12 | PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICES AND DEVICES OBTAINED THEREBY |
DE3030660A DE3030660C2 (en) | 1979-08-13 | 1980-08-13 | Method for the selective diffusion of a dopant into a semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54103052A JPS603772B2 (en) | 1979-08-13 | 1979-08-13 | Manufacturing method for semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5626433A JPS5626433A (en) | 1981-03-14 |
JPS603772B2 true JPS603772B2 (en) | 1985-01-30 |
Family
ID=14343891
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54103052A Expired JPS603772B2 (en) | 1979-08-13 | 1979-08-13 | Manufacturing method for semiconductor devices |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS603772B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4139159A1 (en) * | 1990-11-28 | 1992-06-04 | Mitsubishi Electric Corp | METHOD FOR DIFFUSING N INTERFERENCE POINTS IN AIII-BV CONNECTION SEMICONDUCTORS |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4934018A (en) * | 1972-07-31 | 1974-03-29 | ||
JPS4952967A (en) * | 1972-09-25 | 1974-05-23 |
-
1979
- 1979-08-13 JP JP54103052A patent/JPS603772B2/en not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4934018A (en) * | 1972-07-31 | 1974-03-29 | ||
JPS4952967A (en) * | 1972-09-25 | 1974-05-23 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4139159A1 (en) * | 1990-11-28 | 1992-06-04 | Mitsubishi Electric Corp | METHOD FOR DIFFUSING N INTERFERENCE POINTS IN AIII-BV CONNECTION SEMICONDUCTORS |
Also Published As
Publication number | Publication date |
---|---|
JPS5626433A (en) | 1981-03-14 |
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