JPS6024580B2 - Manufacturing method for semiconductor devices - Google Patents
Manufacturing method for semiconductor devicesInfo
- Publication number
- JPS6024580B2 JPS6024580B2 JP3017380A JP3017380A JPS6024580B2 JP S6024580 B2 JPS6024580 B2 JP S6024580B2 JP 3017380 A JP3017380 A JP 3017380A JP 3017380 A JP3017380 A JP 3017380A JP S6024580 B2 JPS6024580 B2 JP S6024580B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- silver
- semiconductor substrate
- layer
- amorphous chalcogenide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 99
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims description 53
- 150000004770 chalcogenides Chemical class 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- 229910052709 silver Inorganic materials 0.000 claims description 14
- 239000004332 silver Substances 0.000 claims description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 13
- 239000011669 selenium Substances 0.000 claims description 11
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 10
- 150000001875 compounds Chemical class 0.000 claims description 10
- 229910052711 selenium Inorganic materials 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 9
- 239000002245 particle Substances 0.000 claims description 6
- 229910010272 inorganic material Inorganic materials 0.000 claims 1
- 239000011147 inorganic material Substances 0.000 claims 1
- 239000011810 insulating material Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- -1 GaAs is used Chemical group 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 101150109831 SIN4 gene Proteins 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2258—Diffusion into or out of AIIIBV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Silver Salt Photosensitive Materials And Non-Silver Salt Photography (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は、ＧａＡｓ等のｍ−Ｖ族化合物でなる半導体基
板が用いられ、その半導体基板内に所要の不純物の導入
された半導体領域が形成されてなる構成を有する半導体
装置の製法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor having a structure in which a semiconductor substrate made of an m-V group compound such as GaAs is used, and a semiconductor region into which a necessary impurity is introduced is formed in the semiconductor substrate. Regarding the manufacturing method of the device.
ＧａＡｓ等のｍ−Ｖ族化合物でなる半導体基板が用いら
れ、その半導体基板内に所要の不純物の導入された半導
体領域が形成されてなる構成の半導体装置は、その半導
体基板がｍ−Ｖ族化合物であることにより、広く現用さ
れている、シリコンでなる半導体基板が用いられ、その
半導体基板内に所要の不純物の導入された半導体領域が
形成されてなる構成の半導体装置が比し高速応答性を呈
するものである。A semiconductor device has a structure in which a semiconductor substrate made of an m-V group compound such as GaAs is used, and a semiconductor region into which a necessary impurity is introduced is formed in the semiconductor substrate. As a result, a semiconductor device that is widely used today and has a structure in which a semiconductor substrate made of silicon is used and a semiconductor region doped with the required impurities is formed in the semiconductor substrate has a faster response than the other semiconductor devices. It is intended to be presented.
この為近時ｍ−Ｖ族化合物でなる半導体基板が用いられ
、その半導体基板内に所要の不純物の導入された半導体
領域が形成されてなる構成の半導体装置が着目されてい
る。For this reason, attention has recently been focused on a semiconductor device having a structure in which a semiconductor substrate made of an m-V group compound is used, and a semiconductor region into which a necessary impurity is introduced is formed within the semiconductor substrate.
然し乍ら従釆ｍ−Ｖ族化合物でなる半導体基板を対象と
して、その内に所要の不純物の導入された半導体領域を
、所要の不純物濃度を以つて高精度に、しかも簡易に形
成することの出来ると認め得るに十分な方法の提案は未
だなされていないものである。However, it is possible to easily and precisely form a semiconductor region into which a desired impurity is introduced with a desired impurity concentration in a semiconductor substrate made of an m-V group compound. No method has yet been proposed that is sufficient to be accepted.
依って本発明はｍ−Ｖ族化合物でなる半導体基板を対象
として、その内に所要の不純物の導入されてなる半導体
領域を、所望の不純物濃度を以つて高精度に、しかも簡
易に形成することの出来るという新規な工程を含んで、
ｍ−Ｖ族化合物でなる半導体基板が用いられる、その半
導体基板内に所要の不純物の導入された半導体領域が形
成されてなる構成を有する半導体装置の新規な製法を提
供せんとするもので、以下図面を伴なつて詳述する所よ
り明らかとなるであろう。Therefore, the present invention targets a semiconductor substrate made of an m-V group compound, and it is an object of the present invention to form a semiconductor region into which a desired impurity is introduced with high precision and with a desired impurity concentration. Including the new process of being able to
The purpose is to provide a new method for manufacturing a semiconductor device having a structure in which a semiconductor substrate made of an m-V group compound is used, and a semiconductor region into which a necessary impurity is introduced is formed in the semiconductor substrate. It will become clear from the detailed description accompanied by the drawings.
第１図〜第１２図は、発明による半導体装置の製法の実
施例を示し、第１図に示す如き例えばＰ型のＧａＡｓ等
の皿−Ｖ族化合物でなる半導体基板１が予め用意され、
而してその主面２上に、第２図に示す如く、セレン（Ｓ
ｅ）を主成分とせる例えばＳｅ７５原子％、Ｗ２５原子
％でなる非晶質カルコゲナィド層３とその非晶質カルコ
ゲナィド層３上に形成された銀でなる又は銀のハラィド
、カルコゲナィド等の銀を含む層４との積層体でなる無
機フオトレジスト材層５を形成する。1 to 12 show an embodiment of the method for manufacturing a semiconductor device according to the invention, in which a semiconductor substrate 1 made of a plate-V group compound such as P-type GaAs as shown in FIG. 1 is prepared in advance,
Then, on the main surface 2, as shown in FIG.
an amorphous chalcogenide layer 3 mainly composed of e), for example, 75 at. % of Se and 25 at. An inorganic photoresist material layer 5 made of a laminate with layer 4 is formed.
実際上斯る無機フオトレジスト材層５は、その非晶質カ
ルコゲナィド層３を真空蒸着又はスパッタリングによっ
て半導体基板１上に形成し、次に層４を真空蒸着又はス
パッタリングによって又は非晶質カルコゲナィド層３を
銀イオンを含む溶液中に浸薄することによって、非晶質
カルコゲナィド層３上に形成することにより、形成し得
る。次に、第３図に示す如く、無機フオトレジスト材層
５に対する光又は電子線等の加速粒子線６による所要パ
ターンでの露光処理により、無機フオトレジスト材層５
の光又は加速粒子線６にて露光された領域を銀のドープ
された銀ドープ非晶質カルコゲナィド領域７となさしめ
ることにより、無機フオトレジスト材層５に銀のドープ
された銀ドープ非晶質カルコゲナィド層７を形成する。In practice, such an inorganic photoresist material layer 5 is formed by forming the amorphous chalcogenide layer 3 on the semiconductor substrate 1 by vacuum evaporation or sputtering, and then forming the layer 4 by vacuum evaporation or sputtering or by depositing the amorphous chalcogenide layer 3 on the semiconductor substrate 1. It can be formed on the amorphous chalcogenide layer 3 by diluting it in a solution containing silver ions. Next, as shown in FIG. 3, the inorganic photoresist material layer 5 is exposed to light or an accelerated particle beam 6 such as an electron beam in a desired pattern.
By making the region exposed with the light or the accelerated particle beam 6 a silver-doped amorphous chalcogenide region 7, the silver-doped amorphous chalcogenide region 7 is doped with silver. A chalcogenide layer 7 is formed.
次に銀ドープ非晶質カルコゲナィド領域７の形成されて
なる無機フオトレジスト材層５に対する現像処理により
、無機フオトレジスト材層５の銀ドープ非晶質カルコゲ
ナィド領域７以外の領域を半導体基板１上より除去する
。実際上斯る現像処理は、無機フオトレジスト材層５の
銀ドープ非晶質カルコゲナィド領域以外の領域に於ける
非晶質カルコゲナィド層３上に残っている銀又は銀を含
む層４を、第４図に示す如く、希釈王水等のエッチャン
トによるエッチング処理により、非晶質カルコゲナィド
層３上より除去し、次いで銀ドープ非晶質カルコゲナィ
ド領域７が銀のドープされていない非晶資力ルコゲナィ
ド層３に比し化学的耐蝕性が極めて大であることを利用
して、アルカリ溶液又はフッ素系ガスのプラズマによる
エッチング処理により、第５図に示す如く、銀のドープ
されていない非晶質カルコゲナィド層３を半導体基板１
上より除去することでなされている。次に半導体基板１
の主面２上に、第６図に示す如く、銀ドーブ非晶質カル
コゲナィド領域７を覆って例えばＳｉ０２、ＳＩＮ４等
の絶縁材、Ｔｉ、Ｐｔ等の金属でなる耐熱性層８を、真
空蒸着、スパッタリング、プラズマＣＶＤ法等のそれ自
体は公知の種々の方法によって形成する。Next, by developing the inorganic photoresist material layer 5 in which the silver-doped amorphous chalcogenide region 7 is formed, areas other than the silver-doped amorphous chalcogenide region 7 of the inorganic photoresist material layer 5 are removed from the semiconductor substrate 1. Remove. In fact, such a development process removes the silver or silver-containing layer 4 remaining on the amorphous chalcogenide layer 3 in areas other than the silver-doped amorphous chalcogenide area of the inorganic photoresist material layer 5. As shown in the figure, the top of the amorphous chalcogenide layer 3 is removed by etching with an etchant such as dilute aqua regia, and then the silver-doped amorphous chalcogenide region 7 is replaced by an amorphous chalcogenide layer 3 not doped with silver. Taking advantage of its extremely high chemical corrosion resistance, the amorphous chalcogenide layer 3, which is not doped with silver, is etched using an alkaline solution or fluorine gas plasma, as shown in FIG. Semiconductor substrate 1
This is done by removing it from above. Next, semiconductor substrate 1
As shown in FIG. 6, a heat-resistant layer 8 made of an insulating material such as SiO2 or SIN4 or a metal such as Ti or Pt is vacuum-deposited on the main surface 2 of the substrate, covering the silver-doped amorphous chalcogenide region 7, as shown in FIG. It is formed by various methods known per se, such as , sputtering, and plasma CVD.
次に熱処理により、第７図に示す如く、半導体基板１の
銀ドープ非晶質カルコゲナィド領域７下の領域に、その
銀ドープ非晶質カルコゲナィド領域７より、その主成分
たるセレンを熱拡散により不純物として導入せしめて、
セレンによる不純物の導入されたＮ型の半導体領域９を
形成し、斯くて第７図に示す如き半導体基板１の主面２
に銀ドープ非晶質カルコゲナィド領域７を覆って延長せ
る耐熱性層８（尚上述せる熱処理によって銀ドープ非晶
質カルコゲナィド領域７を構成せる材料の全てが半導体
基板１内に導入して、半導体基板１の主面２上に銀ドー
プ非晶質カルコゲナィド領域７が残存していない場合も
あり得、この場合は耐熱性層８は銀ドープ非晶質カルコ
ゲナィド領域７を覆って延長していない）を有し、半導
体基板１内のその主面２側より半導体領域９の形成され
てなる構成を得る。Next, by heat treatment, as shown in FIG. 7, impurities are added to the region below the silver-doped amorphous chalcogenide region 7 of the semiconductor substrate 1 by thermal diffusion of selenium, which is the main component, from the silver-doped amorphous chalcogenide region 7. be introduced as
An N-type semiconductor region 9 doped with selenium impurities is formed on the main surface 2 of the semiconductor substrate 1 as shown in FIG.
The heat-resistant layer 8 extends to cover the silver-doped amorphous chalcogenide region 7 (by the heat treatment described above, all of the materials constituting the silver-doped amorphous chalcogenide region 7 are introduced into the semiconductor substrate 1, and the semiconductor substrate In some cases, the silver-doped amorphous chalcogenide region 7 does not remain on the main surface 2 of the heat-resistant layer 8 (in this case, the heat-resistant layer 8 does not extend to cover the silver-doped amorphous chalcogenide region 7). A structure is obtained in which a semiconductor region 9 is formed in the semiconductor substrate 1 from the main surface 2 side thereof.
次に耐熱性層８が金属でなる場合には、又耐熱性層８が
絶縁材でなる場合であっても必要に応じて、耐熱性層８
に対するエッチング処理により耐熱性層８を半導体基板
１上より除去し、又上述せる熱処理后も第７図に示す如
くに銀ドープ非晶質カルコゲナィド領域７が半導体基板
１上に一部残っている場合はその銀ドープ非晶質カルコ
ゲナィド領域７を半導体基板１上より除去し、斯くて第
８図に示す如き半導体基板１の主面２上より耐熱性層８
及び銀ドープ非晶質カルコゲナィド領域７の全く除去さ
れ、然し乍ら半導体基板１内にその主面２側よりセレン
による不純物の導入された半導体領域の９の形成されて
なる構成を得る。Next, if the heat-resistant layer 8 is made of metal, or even if the heat-resistant layer 8 is made of an insulating material, the heat-resistant layer 8 may be
When the heat-resistant layer 8 is removed from the semiconductor substrate 1 by the etching process, and even after the above-described heat treatment, part of the silver-doped amorphous chalcogenide region 7 remains on the semiconductor substrate 1 as shown in FIG. The silver-doped amorphous chalcogenide region 7 is removed from the semiconductor substrate 1, and the heat-resistant layer 8 is then removed from the main surface 2 of the semiconductor substrate 1 as shown in FIG.
A structure is obtained in which the silver-doped amorphous chalcogenide region 7 is completely removed, but a semiconductor region 9 is formed in which selenium impurities are introduced into the semiconductor substrate 1 from the main surface 2 side.
又第７図に示す如くに熱処理によって半導体基板１内に
半導体領域９を形成して后、次に第８図に示す如くに半
導体基板１上より耐熱性層８及び銀ドープ非晶質カルコ
ゲナィド領域７を全く除去し、次で第９図に示す如く半
導体基板１の主面２上にそれ自体は公知の方法によって
半導体領域９を外部に臨ませる窓１０の穿設されてなる
絶縁層１１を形成し、次で第１０図に示す如く半導体領
域９に、それ自体は公知の方法によって、窓１０を通じ
て絶縁層１１上に延長せる電極乃至配線層１２を連結せ
しめ、斯くて第１０図に示す如き半導体基板１内にその
主面２側より半導体領域９が形成され、その半導体領域
９に電極乃至配線層１２の連結されてなる構成を得る。
更に第６図に示す如くに耐熱性層８を形成する場合に於
て、その耐熱性層８を絶縁材を以つて形成し、而して第
７図に示す如くに熱処理によって半導体基板１内に半導
体領域９を形成する場合、この場合の絶縁材による耐熱
性層８の材質によってその耐熱性層８内に銀ドープ非晶
質カルコゲナィド領域７を構成せる材料が溶け込み、而
してその溶け込み領域が他の領域に比し、耐熱性層８を
除去する為のエッチング処理をなした場合のエッチング
速度が速くなることに鑑み、これを利用して、第７図に
示す如くに半導体基板１１内に半導体領域９を形成して
后、絶縁材でなる耐熱性層８を除去する為のエッチング
処理をなし、次で銀ドープ非晶質カルコゲナィド領域７
が半導体基板１上に一部残っている場合はその銀ドープ
非晶質カルコゲナィド領域７を除去する為のエッチング
処理をなすことによって、第１１図に示す如く、半導体
領域９を外部に臨ませる窓１０を形成されてなる耐熱性
層８による絶縁層１１′を形成し、次で第１２図に示す
如く、それ自体は公知の方法によって、半導体領域９に
、第１０図の場合と同様に窓１１′を通じて絶縁層１１
′上に延長せる電極乃至配線層１２′を連結せしめ、斯
くして第１２図に示す如き半導体基板１内にその主面２
側より半導体領域９が形成され、その半導体領域９に電
極乃至配線層１２′の連結されてなる構成を得る。After a semiconductor region 9 is formed in the semiconductor substrate 1 by heat treatment as shown in FIG. 7, a heat-resistant layer 8 and a silver-doped amorphous chalcogenide region are formed on the semiconductor substrate 1 as shown in FIG. 7 is completely removed, and then, as shown in FIG. 9, an insulating layer 11 is formed on the main surface 2 of the semiconductor substrate 1 by a method known per se, in which a window 10 is formed to expose the semiconductor region 9 to the outside. 10, and then, as shown in FIG. 10, an electrode or wiring layer 12 is connected to the semiconductor region 9, by a method known per se, extending through the window 10 onto the insulating layer 11, thus as shown in FIG. A semiconductor region 9 is formed in the semiconductor substrate 1 from the main surface 2 side, and an electrode or wiring layer 12 is connected to the semiconductor region 9.
Furthermore, when forming the heat-resistant layer 8 as shown in FIG. 6, the heat-resistant layer 8 is formed of an insulating material, and the inside of the semiconductor substrate 1 is heated by heat treatment as shown in FIG. When forming the semiconductor region 9 in the semiconductor region 9, the material forming the silver-doped amorphous chalcogenide region 7 melts into the heat-resistant layer 8 depending on the material of the heat-resistant layer 8 made of an insulating material. Considering that the etching rate for removing the heat-resistant layer 8 is faster than that for other regions, this can be used to remove the inside of the semiconductor substrate 11 as shown in FIG. After forming the semiconductor region 9, an etching process is performed to remove the heat-resistant layer 8 made of an insulating material, and then a silver-doped amorphous chalcogenide region 7 is formed.
If a portion of the silver-doped amorphous chalcogenide region 7 remains on the semiconductor substrate 1, an etching process is performed to remove the silver-doped amorphous chalcogenide region 7, thereby forming a window that exposes the semiconductor region 9 to the outside, as shown in FIG. An insulating layer 11' is formed by the heat-resistant layer 8 formed with the semiconductor region 9, as shown in FIG. Insulating layer 11 through 11'
The electrodes or wiring layer 12' that can be extended upwardly are connected to each other, and thus the main surface 2 is formed in the semiconductor substrate 1 as shown in FIG.
A structure is obtained in which a semiconductor region 9 is formed from the side, and an electrode or wiring layer 12' is connected to the semiconductor region 9.
斯くして第７図にて上述せる構成（但し限定されるので
はないが耐熱性層８が絶縁材による場合が一般的である
）、第８図にて上述せる構成、第１０図にて上述せる構
成、第１２図にて上述せる構成により、ｍ−Ｖ族化合物
であるＰ型の半導体基板１が用いられ、その半導体基板
１内にセレンによる不純物の導入された半導体領域９が
形成されてなる構成を有する目的とせる半導体装置を得
る。Thus, the configuration described above in FIG. 7 (although it is not limited to this, the heat-resistant layer 8 is generally made of an insulating material), the configuration described above in FIG. 8, and the configuration described above in FIG. With the configuration described above and the configuration described above in FIG. 12, a P-type semiconductor substrate 1 made of an m-V group compound is used, and a semiconductor region 9 into which selenium impurities are introduced is formed in the semiconductor substrate 1. To obtain a semiconductor device having the following configuration.
以上にて本発明による半導体装置の製法の実施例が明ら
かとなったが、斯る製法によれば、半導体基板１内に形
成された半導体領域９が、半導体基板１上に形成された
銀ドープ非晶質カルコゲナィド領域７よりその主成分た
るセレンを不純物として導入せしめて得られ、従って半
導体領域９を半導体基板１内に形成するにつき、何等別
途のマスクを要しないものであると共に、銀ドープ非晶
質カルコゲナィド領域７をその主成分以外別途所要の不
純物のドープせしめられたものとして得る必要もないも
のである。The embodiment of the method for manufacturing a semiconductor device according to the present invention has been clarified above, and according to this manufacturing method, the semiconductor region 9 formed in the semiconductor substrate 1 is formed on the semiconductor substrate 1. It is obtained by introducing selenium, which is the main component of the amorphous chalcogenide region 7, as an impurity. Therefore, when forming the semiconductor region 9 in the semiconductor substrate 1, no separate mask is required, and it is not doped with silver. There is no need to obtain the crystalline chalcogenide region 7 doped with any necessary impurities other than its main component.
又銀ドープ非晶質カルコゲナィド領域７が半導体基板１
上に形成された無機フオトレジスト材層５に対する光又
は加速粒子線による所望パターンでの露光処理及びこれ
に続く現像処理にて得られ、而してこの場合の露光処理
に於ける所望パターンが光又は加速粒子線による所望パ
ターンであることにより、その所要パターンが高精度で
得られ、又露光処理后に於ける無機フオトレジスト材層
５の銀ドープ非晶質カルコゲナィド領域７とそれ以外の
領域との間には、無機フオトレジスト材層５が非晶質カ
ルコゲナィド層３とその上に形成された銀又は銀を含む
層４であることにより、格段的に大なる化学的耐蝕性の
差が得られているので、現像処理后に得られる銀ドープ
非晶資力ルコゲナィド領域７が、露光処理に於ける所望
パターンに応じた所要パターンを以つて高精度で得られ
、一方半導体領域９が上述せる如く銀ドープ非晶質カル
コゲナィド領域７よりその主成分たるセレン導入せしめ
て得られるので、半導体領域９が、銀ドープ非晶質カル
コゲナイド領域７に比し１周り大なるパターンを以つて
得られるとしても所要のパターンを以つて高精度で得ら
れるものである。又半導体基板１内に半導体領域９を形
成する熱処理時の時間を制御することにより、半導体領
域９を所要の不純物濃度を以つて形成することが出来る
と共に、半導体領域９の不純物濃度を十分大なるものと
し得るものである。更に半導体領域９を形成する熱処理
が銀ドープ非晶質カルコゲナィド領域７を耐熱性層８に
て覆った状態でなされるので、銀ドープ非晶質カルコゲ
ナイド領域７よりセレンが不必要に外部に飛散すること
がないので、効果的に半導体領域９を形成することが出
来ると共に、不必要に外部より半導体基板１内に不必要
な不純物が導入される擢れも有しないものである。尚更
に半導体基板１上に無機フオトレジスト材層５を形成し
、次にその無機フオトレジスト材層５に対する所望パタ
ーンでの露光処理、続く現像処理をなして銀ドープ非晶
質カルコゲナィド領域７を形成し、次に半導体基板１上
に銀ドープ非晶質カルコゲナィド領域７を覆って耐熱性
層８を形成し、然る后熱処理をなす丈けという簡易な工
程で、半導体基板１に所要の不純物の導入された半導体
領域９を形成することが出来るものである等大なる特徴
を有するものである。尚上述に於ては本発明による半導
体装置の製法につき１つの実施例を述べたに留り、本発
明の精神を脱することなしに種々の変型変更をなし得る
であろう。Further, the silver-doped amorphous chalcogenide region 7 is formed on the semiconductor substrate 1.
The inorganic photoresist material layer 5 formed on the inorganic photoresist material layer 5 is exposed to light or accelerated particle beams in a desired pattern, followed by development processing, and the desired pattern in the exposure processing in this case is obtained by Alternatively, by forming a desired pattern using an accelerated particle beam, the desired pattern can be obtained with high precision, and the silver-doped amorphous chalcogenide region 7 and other regions of the inorganic photoresist material layer 5 can be separated from each other after exposure processing. Since the inorganic photoresist material layer 5 is composed of the amorphous chalcogenide layer 3 and the silver or silver-containing layer 4 formed thereon, a significantly large difference in chemical corrosion resistance can be obtained. As a result, the silver-doped amorphous lucogenide region 7 obtained after the development process can be obtained with high precision in the required pattern according to the desired pattern in the exposure process, while the semiconductor region 9 can be obtained as described above. Since it is obtained by introducing selenium, which is the main component, into the silver-doped amorphous chalcogenide region 7, even if the semiconductor region 9 is obtained with a pattern that is about one size larger than that of the silver-doped amorphous chalcogenide region 7, it is not necessary. This pattern can be obtained with high precision. Furthermore, by controlling the time during the heat treatment to form the semiconductor region 9 in the semiconductor substrate 1, the semiconductor region 9 can be formed with a required impurity concentration, and the impurity concentration of the semiconductor region 9 can be made sufficiently large. It is something that can be assumed. Furthermore, since the heat treatment for forming the semiconductor region 9 is performed with the silver-doped amorphous chalcogenide region 7 covered with the heat-resistant layer 8, selenium from the silver-doped amorphous chalcogenide region 7 is unnecessarily scattered to the outside. Therefore, the semiconductor region 9 can be formed effectively, and there is no possibility that unnecessary impurities are unnecessarily introduced into the semiconductor substrate 1 from the outside. Further, an inorganic photoresist material layer 5 is formed on the semiconductor substrate 1, and then the inorganic photoresist material layer 5 is exposed to light in a desired pattern, followed by a development treatment to form a silver-doped amorphous chalcogenide region 7. Next, a heat-resistant layer 8 is formed on the semiconductor substrate 1 to cover the silver-doped amorphous chalcogenide region 7, and then a heat treatment is performed. It has the characteristics of being able to form the introduced semiconductor region 9. In the above description, only one embodiment of the method for manufacturing a semiconductor device according to the present invention has been described, and various modifications and changes may be made without departing from the spirit of the present invention.
第１図〜第１２図は本発明による半導体装置の製法の実
施例を示す順次の工程に於ける略線的断面図である。
図中１‘まｍ−Ｖ族化合物でなる半導体基板、２は主面
、３は非晶質カルコゲナィド層、４は銀又は銀を含む層
、５は無機フオトレジスト材層、６は光又は加速粒子線
、７は銀ドープ非晶質カルコゲナィド領域、８は耐熱性
層、９は半導体領域、１０及び１０′は窓、１１及び１
１′は絶縁層、１２及び１２′は電極乃至配線層を夫々
示す。
第１図第２図
第３図
第４図
第５図
第６図
第７図
第８図
第９図
第１０図
第１１図
第１２図1 to 12 are schematic cross-sectional views showing successive steps of an embodiment of the method for manufacturing a semiconductor device according to the present invention. In the figure, 1' is a semiconductor substrate made of an m-V group compound, 2 is a main surface, 3 is an amorphous chalcogenide layer, 4 is silver or a layer containing silver, 5 is an inorganic photoresist material layer, and 6 is light or acceleration particle beam, 7 is a silver-doped amorphous chalcogenide region, 8 is a heat-resistant layer, 9 is a semiconductor region, 10 and 10' are windows, 11 and 1
1' is an insulating layer, and 12 and 12' are electrodes or wiring layers, respectively. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12
Claims (1)
成分とせる非晶質カルコゲナイド層と該非晶質カルコゲ
ナイド層上に形成された銀でなる又は銀を含む層との積
層体でなる無機フオトレジスト材層を形成する工程と、
該無機フオトレジスト材層に対する光又は加速粒子線
による所望パターンでの露光処理により、上記無機フオ
トレジスト材層に銀のドープされた銀ドープ非晶質カル
コゲナイド領域を形成する工程と、 該銀ドープ非晶質
カルコゲナイド領域の形成された無機フオトレジスト材
層に対する現像処理により当該無機フオトレジスト材層
の上記銀ドープ非晶質カルコゲナイド領域以外の領域を
上記半導体基板上より除去する工程と、 上記半導体基
板上に上記銀ドープ非晶質カルコゲナイド領域を覆つて
耐熱性層を形成する工程と、 熱処理により上記半導体
基板内に上記銀ドープ非晶質カルコゲナイド領域よりそ
の主成分たるセレンを不純物として導入せしめて上記半
導体基板内にセレンによる不純物の導入された半導体領
域を形成する工程とを含む事を特徴とする半導体装置の
製法。1. An inorganic material consisting of a laminate of an amorphous chalcogenide layer containing selenium as a main component and a layer made of silver or containing silver formed on the amorphous chalcogenide layer on a semiconductor substrate made of a III-V group compound. forming a layer of photoresist material;
forming a silver-doped amorphous chalcogenide region doped with silver in the inorganic photoresist material layer by exposing the inorganic photoresist material layer to light or an accelerated particle beam in a desired pattern; removing a region of the inorganic photoresist material layer other than the silver-doped amorphous chalcogenide region from the semiconductor substrate by developing the inorganic photoresist material layer in which the crystalline chalcogenide region is formed; forming a heat-resistant layer covering the silver-doped amorphous chalcogenide region; and introducing selenium, the main component of the silver-doped amorphous chalcogenide region, into the semiconductor substrate as an impurity by heat treatment, thereby forming the semiconductor substrate. 1. A method for manufacturing a semiconductor device, comprising the step of forming a semiconductor region into which an impurity of selenium is introduced in a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3017380A JPS6024580B2 (en) | 1980-03-10 | 1980-03-10 | Manufacturing method for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3017380A JPS6024580B2 (en) | 1980-03-10 | 1980-03-10 | Manufacturing method for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56126916A JPS56126916A (en) | 1981-10-05 |
| JPS6024580B2 true JPS6024580B2 (en) | 1985-06-13 |
Family
ID=12296352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3017380A Expired JPS6024580B2 (en) | 1980-03-10 | 1980-03-10 | Manufacturing method for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6024580B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4139159A1 (en) * | 1990-11-28 | 1992-06-04 | Mitsubishi Electric Corp | METHOD FOR DIFFUSING N INTERFERENCE POINTS IN AIII-BV CONNECTION SEMICONDUCTORS |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6653193B2 (en) | 2000-12-08 | 2003-11-25 | Micron Technology, Inc. | Resistance variable device |
| US6638820B2 (en) | 2001-02-08 | 2003-10-28 | Micron Technology, Inc. | Method of forming chalcogenide comprising devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and chalcogenide comprising devices |
| US6727192B2 (en) * | 2001-03-01 | 2004-04-27 | Micron Technology, Inc. | Methods of metal doping a chalcogenide material |
| US6818481B2 (en) | 2001-03-07 | 2004-11-16 | Micron Technology, Inc. | Method to manufacture a buried electrode PCRAM cell |
| US6734455B2 (en) | 2001-03-15 | 2004-05-11 | Micron Technology, Inc. | Agglomeration elimination for metal sputter deposition of chalcogenides |
| US6737312B2 (en) | 2001-08-27 | 2004-05-18 | Micron Technology, Inc. | Method of fabricating dual PCRAM cells sharing a common electrode |
| US6784018B2 (en) | 2001-08-29 | 2004-08-31 | Micron Technology, Inc. | Method of forming chalcogenide comprising devices and method of forming a programmable memory cell of memory circuitry |
| US6646902B2 (en) | 2001-08-30 | 2003-11-11 | Micron Technology, Inc. | Method of retaining memory state in a programmable conductor RAM |
| US20030143782A1 (en) | 2002-01-31 | 2003-07-31 | Gilton Terry L. | Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures |
| US7151273B2 (en) | 2002-02-20 | 2006-12-19 | Micron Technology, Inc. | Silver-selenide/chalcogenide glass stack for resistance variable memory |
| US7015494B2 (en) | 2002-07-10 | 2006-03-21 | Micron Technology, Inc. | Assemblies displaying differential negative resistance |
| US6831019B1 (en) | 2002-08-29 | 2004-12-14 | Micron Technology, Inc. | Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes |
| US6813178B2 (en) | 2003-03-12 | 2004-11-02 | Micron Technology, Inc. | Chalcogenide glass constant current device, and its method of fabrication and operation |
| US7583551B2 (en) | 2004-03-10 | 2009-09-01 | Micron Technology, Inc. | Power management control and controlling memory refresh operations |
| US7354793B2 (en) | 2004-08-12 | 2008-04-08 | Micron Technology, Inc. | Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element |
-
1980
- 1980-03-10 JP JP3017380A patent/JPS6024580B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4139159A1 (en) * | 1990-11-28 | 1992-06-04 | Mitsubishi Electric Corp | METHOD FOR DIFFUSING N INTERFERENCE POINTS IN AIII-BV CONNECTION SEMICONDUCTORS |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56126916A (en) | 1981-10-05 |
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