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JPS59232432A - 混成集積回路の製造方法 - Google Patents

混成集積回路の製造方法

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Publication number
JPS59232432A
JPS59232432A JP58107126A JP10712683A JPS59232432A JP S59232432 A JPS59232432 A JP S59232432A JP 58107126 A JP58107126 A JP 58107126A JP 10712683 A JP10712683 A JP 10712683A JP S59232432 A JPS59232432 A JP S59232432A
Authority
JP
Japan
Prior art keywords
layer
integrated circuit
hybrid integrated
bonding
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58107126A
Other languages
English (en)
Inventor
Giichi Saito
斉藤　義一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58107126A priority Critical patent/JPS59232432A/ja
Publication of JPS59232432A publication Critical patent/JPS59232432A/ja
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （ａ）発明の技術分野 本発明は混成集積回路の製造方法、　ｌｌ？にボンディ
ング強度を高めるボンティングパッド形成法に関する。
（ｂ）技術の背景 基板上Ｖζ回路素子を形成及び搭載してなる混成集積回
路において、半導体回路素子や外部接続用リード端子等
の搭載及び搭載回路素子の電極を形成回路素子に接続す
る手段として、熱圧着やワイヤボンディングが一般に行
われており、前記基板上にはそのだめのボンティングパ
ッドが形成されている。
（ｃ）　　従来技術と問題点 第１図は従来方法で形成されたタンタル薄膜混成集積回
路のボンティングパッドに外部リード端子を接続した部
分の側面図である。
第１図において、１はアルミナ基板、２は基板１の表面
に被着したＴａｘＮ層、３はＴａｚＮ層２の上にパター
ン形成しだＮｉ−０ｒ層、４はＮｉ−Ｃｒ層３の上に蒸
着形成したＡｕ層（パッド基層）５はＡｌ１層４の上に
めっき形成しブｊＡｕ層であり。
Ａｕめっきした金属細線（又はＡｕ細線）ＶＣてなるリ
ード端子６の一端がＡｕ層５の上に熱圧着法でボンディ
ングされている。
このように構成されたパッドのＡｕ層５は、細線６との
Ａｌｌ相互拡散を確保するため、一般に３　ｔｒ　ｍ〜
５　／１ｍの均一厚さに被着している。従って。
多数のボンディングパラｉ・有する集積回路を多数個製
造するとき、高価であり有限の天然資源である金（八Ｕ
）の消費量は極めて大量になるとともに、ボンディング
強度を高める技術的努力が限界に達しており、それらの
新規対策が望まれていた・（ｄ、）　　発明の目的 本発明の目的は、上記問題点に鑑みてＡｌｌの消費量を
低減させ、同時にボンティング強度を高めることである
６ （ｅｌ　　発明の溝成 上記目的は、ボンディングパラｔ′のクシ、くとも表面
を平面視網目状の凹凸に分割形成することを特徴とした
混成集積回路の製造方法により達成される。
（ｆ＋　　発明の実施例　　・ 以下５図面を用いて本発明方法の実施例を説明する。
第２図は本発明方法の一実施例に係わりタンタル薄膜混
成集積回路のボンディングパソド（Ｃ外部リード端子を
接続した部分の側面図、第３図は外部リード端子を接続
してない前記）Ｚ・ノドの平面図第４図は前記パッドの
ΔＵめつき層を被着する実施例を説明するだめの側面図
でるる。
第１図と共通可能な部分に同一符号（１，２，３，４）
を用いた第２図において、基板１０所定部上面に積層さ
れたＴａｌＮ層２とｔｙｔ−ｃｒＪ１３と蒸着ＡｕＪｆ
ｉ　４の上にめっき形成されたＡｌ１層１５は第３図に
示す如く、角柱形状の突起１５ａ　が多数個（図は３６
個）配列された網目状であり、その上にＡｌｌめっきし
た金属細線（又（、」、Ａｕ細線）Ｋてなるリード端子
１６の一端が熱圧着法でボンディングきれている。ただ
し、リード端子１６の凹部１６ａｊ：ｊボンテイングウ
エツンで押しつぶされてできたものでらり１凹部１６８
の近傍の下方に位置する突起１５ａは、リード端子１６
の表面となじむように塑性変形し、リード端子１６にボ
ンディングされている。従って、第１図のリード端子６
と第２図のリード端子Ｊ６とを同じ条件でボンディング
したとき、リード端子６かＡｕ層５に接続される面積よ
りも、リード端子１６とＡｕｌ鱗工５とが接続される面
積の方が大きくなる。
第３図において、蒸着Ａｕ層４の上ｙｃめつき升成され
突起１５ａの断面寸法はＷ　Ｘ　Ｗとし、そオらの列方
向及び行方向間隔は１，７・である。セしてνと、υは
１例えばリード端子】６の直径（又は幅）が２００　ｔ
ノｍのときそれぞれ５０　ａ　ｍ　ＶＣするが如く五定
される 第４図において、基板１及び蒸着Ａｕ層４の−・に被着
；ｇ７’Ｌ／ｊし／ストＩｆ＜１７．１．７　ａは、複
数個ＱＡｌｌ突起１５ＩＬ（Ａｕｌψ１１５）　　をめ
っき形成さ→るためのものであり、それらは各突起１５
ａにヌ向する網目状パターンが設けられたマスクを用し
たフォトリソグラクイ技術により形成されてい２そして
突起１５ａは、レジスト層１７と１７ａＱ間隙を埋めて
、Ａｌ１１け４の上（（めっき被着され２なか２、ト記
実施例では基板−Ｆのパッドに外部引続用リード端子を
ごム圧着法で搭載しメこ一例であ２が、他の回路素子の
搭載例えは半導体素子を・フコ−ツボ／ティングすると
き、及び超音波法などイ１の方法での搭載等にも本発明
方法が適用されることをイτ１記する。
多　　（ｇ）発明の効果 ｔ　　　　以上説明した如く本発明によれし１１．カミ
ンテインｌ　　　グバツＦが相手の面になじみ易く、そ
のことによ−ってボンティング面積が拡がる等に」：す
、γＦンティング強度は従来のものよ！７１０〜２０係
強くなったのみたらず、被着するＡｕの月が減少するた
ヒ　　　め混成集積回路のコス（・が低減し、さらに網
目状、　　　のバク−／を設けたマスクを用いて本発明
方法にセ　　　係わるレジスト層を形成することにより
、工程をづ　　　増すことなく本発明が製品に適用され
る効イは大きい・・ ５゜　４、図面の簡単な説明 、　　　　第１図は従来方法で形成されたタンクルジ薄
１１Ｊ（混成集積回路のパッドに外部リード端子をポン
ティ良　　　ングしだ部分の側面図、第２図は本発明方
法の一実施例に係わりタンタル薄膜混成集積回路のツク
′ノドに外部リード端子をボンティングＬ７だ部分の側
は　　　面図、第３図は第２図に示しだツクノドの前記
７にンデインク前におりる平面図、第４図は８￥２図及
び第３図に示（〜だパッドのＡｌ１めつ＠層を被着する
実施例を説明するだめの’Ｉｔ”ＩＩ面図である、図に
ふいて、１は基板、２１＜ｌ、ＴａｘＮ層、３はＮ　１
−Ｃｒ層、４ｉ＋：蒸着Ａｕｌ済、５．１５に！、めっ
きＡｌ１層、１５ｅ、ＩｔよＡｕ層Ｊ５を構成するＡｕ
突起、１７゜１７８（弓しジストパターンヲ示ス・ 代理人　弁理士　松岡宏四西−「Ｉ？、１．ｊ（＋、−
，・′ｌ１１

Claims (2)

    【特許請求の範囲】
  1. （１）ボンディングバットの少なくとも表面を平面視網
    目状の凹凸に分割形成することを特徴とした混成集積回
    路の製造方法。
  2. （２）前記網目状にパターン形成されたマスクを用いて
    パッド基層の上に網状のレジストハターンを形成し、該
    レンストパターンの網目間隙を埋めるめっき層を被着す
    ることを４？徴とした前記特許請求の範囲第１項に記載
    した混成集積回路の製造方法・
JP58107126A 1983-06-15 1983-06-15 混成集積回路の製造方法 Pending JPS59232432A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58107126A JPS59232432A (ja) 1983-06-15 1983-06-15 混成集積回路の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58107126A JPS59232432A (ja) 1983-06-15 1983-06-15 混成集積回路の製造方法

Publications (1)

Publication Number Publication Date
JPS59232432A true JPS59232432A (ja) 1984-12-27

Family

ID=14451150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58107126A Pending JPS59232432A (ja) 1983-06-15 1983-06-15 混成集積回路の製造方法

Country Status (1)

Country Link
JP (1) JPS59232432A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087756A (en) * 1997-08-11 2000-07-11 Murata Manufacturing Co., Ltd. Surface acoustic wave
US6414415B1 (en) 1999-02-18 2002-07-02 Murata Manufacturing Co., Ltd. Surface acoustic wave device and method for manufacturing the same
US7102461B2 (en) * 2003-07-28 2006-09-05 Tdk Corporation Surface acoustic wave element, surface acoustic wave device, surface acoustic wave duplexer, and method of manufacturing surface acoustic wave element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087756A (en) * 1997-08-11 2000-07-11 Murata Manufacturing Co., Ltd. Surface acoustic wave
US6414415B1 (en) 1999-02-18 2002-07-02 Murata Manufacturing Co., Ltd. Surface acoustic wave device and method for manufacturing the same
US7102461B2 (en) * 2003-07-28 2006-09-05 Tdk Corporation Surface acoustic wave element, surface acoustic wave device, surface acoustic wave duplexer, and method of manufacturing surface acoustic wave element

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