JPS59172796A - Method of producing printed circuit board - Google Patents
Method of producing printed circuit boardInfo
- Publication number
- JPS59172796A JPS59172796A JP4767383A JP4767383A JPS59172796A JP S59172796 A JPS59172796 A JP S59172796A JP 4767383 A JP4767383 A JP 4767383A JP 4767383 A JP4767383 A JP 4767383A JP S59172796 A JPS59172796 A JP S59172796A
- Authority
- JP
- Japan
- Prior art keywords
- catalyst
- laminate
- copper
- range
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、銅張り積層板を用いて、スル−ホール部など
の必要な部分のみに選択的に無電解め―きを析出させる
経済的かつ作業性に優れたブリント回路板に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention is an economical and highly workable blind that uses a copper-clad laminate to selectively deposit electroless plating only on necessary areas such as through holes. Concerning circuit boards.
周知の如く、従来プリント回路板の製造方法の主流はエ
ツチドフォイル法が一般的でおる。しかし、近年プリン
ト回路板の高密度化に伴い、従来のエツチドフォイル法
では製造工程が複雑な上、エツチング時のアンダーカッ
トや電気めっきに伴うめっき厚の不均一による回路自身
の寸法精度が悪いばかりでなく、オーバーハングによる
ブリッジなどのために、その工業的な生産が難しくなっ
てきている。As is well known, the mainstream method for manufacturing printed circuit boards has been the etched foil method. However, as printed circuit boards have become denser in recent years, the conventional etched foil method has not only complicated the manufacturing process but also degraded the dimensional accuracy of the circuit itself due to undercuts during etching and uneven plating thickness due to electroplating. In addition, overhanging bridges and other factors have made it difficult to produce them industrially.
したがって、最近は電気めっきに伴うめっき厚みの不均
一を回避し均一なめっき厚み″を得ることのできる無電
解めっきを主流とした高密度化に対応すべく種々の方法
が提案されている。Therefore, recently, various methods have been proposed in order to cope with the increase in density, mainly using electroless plating, which can avoid the non-uniformity of plating thickness caused by electroplating and obtain a uniform plating thickness.
その一つとしてアディティブ法があるが、高価な特殊基
材の使用や表面粗化液による公害問題などあり、また、
基材と回路部との密着性や使用する接着剤のコスト面な
どを考え合わせると、やはり銅張り積層板をベースにし
たものがこれからも主流になってゆくものと考えられる
。One of these methods is the additive method, but it has problems such as the use of expensive special base materials and pollution problems caused by surface roughening liquid.
Considering the adhesion between the base material and the circuit part and the cost of the adhesive used, it is thought that copper-clad laminate-based products will continue to become mainstream.
例えば、銅張り積層板にスルーホール
必要な回路及びスルーホール部をマスクし、余分な銅を
エツチングで溶解除去し、次いでスルーホール部を含む
積層版表面全体に触媒付与を施し、スルーホール部など
の所望する部分のみに無電解めっきを施すことにより回
路を形成するプリント回路板の製造が考えられる。For example, in a copper-clad laminate, circuits and through-holes that require through-holes are masked, excess copper is dissolved and removed by etching, and then a catalyst is applied to the entire surface of the laminate including the through-holes. It is conceivable to manufacture a printed circuit board in which a circuit is formed by applying electroless plating only to desired portions of the circuit.
しかし、この方法においては、吸着させた触媒の量が多
い場合、回路間の絶縁抵抗の低下を招き、極端に回路間
の狭い部分など短絡の原因となる。However, in this method, if the amount of adsorbed catalyst is large, the insulation resistance between the circuits will decrease, causing short circuits in extremely narrow areas between the circuits.
そこで、例えば(1)特開昭54−11965号の発明
では、銅張り積層板上の銅箔を選択エツチングにより所
望回路を形成した後、形成された回路の所定の位置にス
ルーホールを形成し、次いでこのスルーホール部を含み
回路形成全体上に無電解めっき前処理層を形成し、その
後回路形成全体の無電解めっき前処理層を機械的に除去
し、前記の無電解めっき前処理層を形成したスルーホー
ル部とその周囲の回路部以外にソルダーレジスト膜を形
成し、然る後スルーホール部とその周囲の回路部に無電
解めっき層を形成させるプリント回路板の製造方法が提
案されている。For example, (1) the invention disclosed in JP-A-54-11965 involves forming a desired circuit by selectively etching the copper foil on the copper-clad laminate, and then forming through holes at predetermined positions in the formed circuit. Next, an electroless plating pretreatment layer is formed on the entire circuit formation including this through hole portion, and then the electroless plating pretreatment layer of the entire circuit formation is mechanically removed, and the electroless plating pretreatment layer is removed. A method of manufacturing a printed circuit board has been proposed in which a solder resist film is formed on areas other than the formed through-holes and the circuit area around them, and then an electroless plating layer is formed on the through-hole areas and the circuit areas around them. There is.
また(2)特開昭50 − 155965号の発明では
、銅張り積層板にスルーホールを形成し、ヌルーホール
部穴内を含む全表面に無電解めっき用活性化物質の層を
形成させ、活性化物質で被覆された板の表面に光硬化フ
ィルム状のレジストを密着させ、スルーホーlし部分と
印刷回路になるべき部分とが残るように露光現像し、露
出した銅箔をエツチング除去した後、露呈した無電解め
っき用活性化物質−に無電解めっきを行なうプリント回
路板の製造方法が提案されている。In addition, (2) the invention disclosed in JP-A-50-155965 forms through-holes in a copper-clad laminate, and forms a layer of an activating substance for electroless plating on the entire surface including the inside of the null hole. A resist in the form of a photocurable film was adhered to the surface of the plate coated with copper foil, exposed and developed so that the through-hole area and the area that would become the printed circuit remained, and the exposed copper foil was removed by etching. A method of manufacturing a printed circuit board has been proposed in which electroless plating is performed using an activator for electroless plating.
さらにまた同様に(3ン銅張シ積層板にスルーホーpを
形成し、スμmホール部を含んだ回路部以外をアルカリ
可溶性インクでマスクし、次いで無電解めっき用活性化
を行なった後、前記インクを除去し活性化層の残ってい
るヌ/レーホール部及び回路部に力((電解めっきを行
なうプリント回路板の製造方法などが提案されている。Furthermore, in the same manner (through-holes P were formed in a 3-inch copper-clad laminate, areas other than the circuit area including the μm hole portions were masked with alkali-soluble ink, and then activation for electroless plating was performed, as described above). A method for manufacturing printed circuit boards has been proposed in which the ink is removed and the activated layer remains on the holes and circuit areas using electrolytic plating.
しかしながら、上記従来方法のいずれも部分的に活性化
層を残存させ、そ9部分のみを無電解めっきによりめっ
き膜を形成させようとするものであるが、それぞれの製
造方法において活性化層を除去するための余分な工程が
1つ増えるため工程が複雑化し、実用的な方法でなく、
捷たそれぞれの活性化層除去方法において下記の欠点を
有している。However, in all of the above conventional methods, the activation layer remains partially and a plating film is formed only on the 9 parts by electroless plating, but in each manufacturing method, the activation layer is removed. The process becomes complicated due to the addition of one extra step, and it is not a practical method.
Each of the methods for removing the activated layer has the following drawbacks.
(1)の方法においては、特に回路間隔が狭くなった部
分において触媒物質を除去することが困難となるばかシ
でなく、例えば機械的研摩を用いた場合、回路部から非
常に微細な「ひけ」が発生し回路間の短.絡が生じる。Method (1) does not make it difficult to remove the catalyst material, especially in areas where the circuit spacing is narrow; for example, if mechanical polishing is used, very fine "sink marks" can be removed from the circuit area. ” occurs, causing a short circuit between the circuits. A conflict occurs.
また、(2)の方法においては、高密度化に伴うファイ
ンな回路を形成する場合、使用するレジストと銅箔との
間に活性化物質層が存在するため、例えば光硬化型フイ
ルム状レジストを用いた場合、レジ7トと銅箔との密着
性に欠け、現像もしくはエツチング時に回路上のレジス
トが流れ、その結果エツチングレジストとしての役目を
果たさなくなり、所望する回路の形成が困難となる。In addition, in method (2), when forming fine circuits due to high density, there is an activated material layer between the resist used and the copper foil, so for example, a photocurable film resist is used. When used, the adhesiveness between the resist and the copper foil is poor, and the resist on the circuit flows during development or etching, and as a result, it no longer functions as an etching resist, making it difficult to form the desired circuit.
さらにまた、(3)の方法においては、ヌル−ホール部
内壁に往々にしてインクが付着し活性化に・1が部分的
に形成されないことがある。また銅張シ積層板全面にイ
ンクでマスク全形成し、その後ヌル−ホール部を設ける
場合においても、ドリルによる穴あけあるいは金型によ
る打抜き時にドリル及び金型のビンにインクが付着し、
さらにそれがスルーホール内壁に付着しスミャーに似た
現象を起こし、部分的に無電解めっきが析出しない場合
や析出しても無電解めっきとの密着状聾が感化する。Furthermore, in the method (3), ink often adheres to the inner wall of the null-hole portion, and .1 may not be partially formed during activation. In addition, even when a mask is completely formed on the entire surface of a copper-clad laminate with ink, and then a null hole is provided, ink may adhere to the drill and the bottle of the mold during drilling with a drill or punching with a mold.
Furthermore, it adheres to the inner wall of the through hole and causes a phenomenon similar to smear, and if the electroless plating does not deposit partially or even if it does, the contact with the electroless plating becomes sensitive.
以上の如く、前記に示した種々のプリント回路板の製造
方法は実用性に乏しく、製品を工業的に生産することは
不可能である。As described above, the various printed circuit board manufacturing methods described above are impractical, and it is impossible to industrially produce the products.
そこで、本発明は上記従来方法の欠点を鑑み、これを解
消して工程が簡略化できかつ極めて信頼性が高く経済的
に安価な高密度プリント回路板を容易に生産し得る製造
方法を見い出した。Therefore, in view of the above-mentioned drawbacks of the conventional methods, the present invention has discovered a manufacturing method that can simplify the process and easily produce extremely reliable and economically inexpensive high-density printed circuit boards. .
即ち、本発明は銅張シ積層板に穴あけを施した後、スル
ーホール部及び所望の回路部をマスクし、回路部以外の
余分な銅箔をエツチングにより溶解除去するか、或いは
所望回路以外の銅箔をエツチングし、形成された回路の
)31r定位置にスルーホー)Vを形成するかのどちら
かを行なったのち、ヌル−ホール内壁を含む積層板表面
全体に0.15〜4d以下の触媒を吸着させる。さらに
、前記積層板のスルーホール部もしくはめっきの必要な
箇所以外にソルダーレジスト膜を形成後、無電解めっき
浴に浸漬し、スルーホール部もしくは回路上にめっきを
施すか、もしくは必要によりソルダーレジスト膜のかわ
りに光硬化型フィルム状レジストで無電解めっきの必要
でない箇所をマスクし、無電解めっき浴に浸漬し、めっ
きを施した後、ソルダーレジスト膜を形成するという工
程を持つプリント回路板の製造方法である。That is, in the present invention, after drilling a hole in a copper-clad laminate, masking the through-hole portion and the desired circuit portion, and dissolving and removing the excess copper foil other than the circuit portion, or removing the excess copper foil other than the desired circuit portion. After etching the copper foil and forming through-holes (V) at fixed positions of the formed circuit, a catalyst of 0.15 to 4 d or less is applied to the entire surface of the laminate including the inner wall of the null-holes. to be adsorbed. Furthermore, after forming a solder resist film on the through-hole portions of the laminate or other areas other than those that require plating, it is immersed in an electroless plating bath and plated on the through-hole portions or circuits, or if necessary, a solder resist film is formed on the through-hole portions or circuits. Instead, the manufacturing of printed circuit boards involves the process of masking areas that do not require electroless plating with a photocurable film resist, immersing them in an electroless plating bath, plating, and then forming a solder resist film. It's a method.
以下本発明を図面を用いて詳細に説明する。The present invention will be explained in detail below using the drawings.
第1図は、本発明に使用する銅張り積層板の縦断面図を
示す。この槓J田板は市販されているもの全て使用可能
である。例えば、紙エポキシ銅張り積層板、ガラスエポ
キシ銅張り積層板、コンボジフト銅張シ積層板、トリア
ジン鋼張シ積層板を用いることができる。また、銅箔の
厚みも一般に入手可能な18.36.70μmのうち、
いずれも使用可能であるが、現在高密度化が進展してい
るため、回路間隔及び回路幅の狭いものを形成する上に
おいて、銅箔の厚みは18μmが好ましい。FIG. 1 shows a longitudinal cross-sectional view of a copper-clad laminate used in the present invention. All commercially available katana plates can be used. For example, a paper-epoxy copper-clad laminate, a glass-epoxy copper-clad laminate, a combo dift copper-clad laminate, and a triazine steel-clad laminate can be used. In addition, the thickness of copper foil is 18.36.70 μm which is generally available.
Any of these can be used, but since high density is currently progressing, the thickness of the copper foil is preferably 18 μm in order to form circuits with narrow circuit spacing and circuit width.
次に回路として必要な部品挿入用、並びに表裏導通用の
穴をあける。これを示すのが第2図である。穴あけはド
リル及び金型による打抜きの両方共使用可能であるが、
同一品種の穴あけが多量である場合には金型による打抜
きが有利であり、少量である場合にはドIJ )しの方
が有利である。Next, holes are made for inserting the components necessary for the circuit and for conducting between the front and back sides. FIG. 2 shows this. For drilling, both drilling and punching with a die can be used,
If a large number of holes of the same type are to be punched, punching with a die is advantageous, and if a small amount is to be punched, a die-cutting method is more advantageous.
第8図及び第4図はエツチング工程を示す。エツチング
工程で用いるレジストは、アルカリ及°び有機溶剤可溶
性インク、または光硬化型フイルム状レジストの2種が
考えられる。しかし、インクはピンホール、回路寸法精
度が悪いという問題があり、また時々スルーホール内壁
にインクが付着し、インク剥膜時に除去しりこぐいため
、エツチング用レジストとして使用しがたく、むしろ、
光硬化型フィルム状レジストいわゆるフォトレジストが
好ましい。フォトレジストとしては、例えばデュポン社
製リストン、ダイナケム社製ラミナーがあり、このうち
いずれを用いてもよい。また、エツチング液は、アルカ
リ性エツチング液、塩化第二鉄、塩化第二銅などが挙げ
られるが、エツチングレジストがフォトレジストであり
、公害等の問題により廃液処理が可能で、再生可能な工
、ノチング液でなければならないことより、エツチング
液は塩化第二銅が好ましい。FIGS. 8 and 4 show the etching process. There are two types of resists used in the etching process: alkaline and organic solvent soluble inks and photocurable film resists. However, the ink has problems with pinholes and poor circuit dimensional accuracy, and sometimes the ink adheres to the inner wall of the through hole and is difficult to remove when the ink film is peeled off, making it difficult to use as an etching resist.
A photocurable film resist, so-called photoresist, is preferred. Examples of the photoresist include Riston manufactured by DuPont and Laminar manufactured by Dynachem, and any of these may be used. Etching liquids include alkaline etching liquid, ferric chloride, cupric chloride, etc., but the etching resist is a photoresist, and waste liquid can be disposed of due to problems such as pollution. Since the etching solution must be a liquid, cupric chloride is preferably used as the etching solution.
なお本発明においては、上記の方法を用いて、エツチン
グにより回路を形成した後、穴あけを行なうという工程
でもよい。In the present invention, the above method may be used to form the circuit by etching, and then the process may be performed by drilling holes.
次に無電解めっきの前処理を行なう。これを示したのが
第6図である。無電解めっきについては、無電解銅めっ
き、無電解ニッケルめっき、無電解金めっきなどがある
がめつき浴が異なるだけで他のめっき前処理工程は同一
であるので、ここでは無電解銅めっきを用いた方法につ
いて説明する。Next, pretreatment for electroless plating is performed. FIG. 6 shows this. Regarding electroless plating, there are electroless copper plating, electroless nickel plating, electroless gold plating, etc., but the only difference is the plating bath, and the other plating pretreatment steps are the same, so we will use electroless copper plating here. I will explain how I did it.
1ず、最初に脱脂であるが、有機溶剤またはアルカリ性
水溶液を使用する。例えば、トリクロルエチレン、0.
1〜5mol/gの水酸化ナトリウム水溶液、シブレイ
社製γルギレートまたはシェーリング社製りリーナーセ
モユリガント902のうちいずれを用いてもよい。1. First, degreasing is performed using an organic solvent or alkaline aqueous solution. For example, trichlorethylene, 0.
Any one of a 1 to 5 mol/g aqueous sodium hydroxide solution, γ Lugyrate manufactured by Sibley, or Liner Semoyligant 902 manufactured by Schering Co., may be used.
次にジグレイ社製コンディショナー1160を用いてス
ルーホール
面を施してもよい。A through-hole surface may then be applied using Conditioner 1160 manufactured by GiGray.
さらに、銅表面のソフトエツチングを行なう。Furthermore, soft etching is performed on the copper surface.
この工程には、100〜250Vlの過妨酸アンモニウ
ムもしくは1. 0 〜4, O mol/43の硫酸
、0.5〜2、 5 mol/71の過酸化水素から成
る混合水溶液のうちいず几を用いてもよい。This step requires 100-250 Vl of ammonium peroxide or 1. Any mixed aqueous solution consisting of 0 to 4.0 mol/43 sulfuric acid and 0.5 to 2.5 mol/71 hydrogen peroxide may be used.
最後に、触媒付与を行なう。ここでいう触媒付与とは、
触媒となりうる金属イオンを含む溶液に積層板を浸漬し
て、積層板上に金属イオンを吸着させ、次に触媒となる
金属イオンを金属に猫元可能な液に前記積層板を浸漬す
ることにより、前記積層板上に触媒を吸着させる方法で
ある。具体的には、触婬となりうる金属イオンを含む水
溶液は、PdC#z SnC/+2HCII ( :
l ロイドタイプ)、P+lCL SnCgz N
hCe (コロイドタイプ)、パラジウム有機錯塩化合
物の8種があり、このうちいずれを用いてもよい。また
、金属イオンを金属に還元可能な液は、硫酸・シュウ酸
から成る水溶液、もしくは水酸化ナトリウムまたは炭酸
ナトリウム等のアルカリ性水酸化物とホウ水素化合物か
ら成る水溶液の2種があり、このうちいずれを用いても
よい。Finally, a catalyst is applied. What is meant by catalyzing here?
By immersing a laminate in a solution containing metal ions that can act as a catalyst, the metal ions are adsorbed onto the laminate, and then by immersing the laminate in a solution that allows the metal ions that can act as a catalyst to be absorbed into the metal. , a method in which a catalyst is adsorbed onto the laminate. Specifically, an aqueous solution containing metal ions that can act as an catalytic agent is PdC#z SnC/+2HCII (:
l Lloyd type), P+lCL SnCgz N
There are eight types of hCe (colloid type) and palladium organic complex salt compounds, any of which may be used. There are two types of liquids that can reduce metal ions to metals: an aqueous solution consisting of sulfuric acid or oxalic acid, and an aqueous solution consisting of an alkaline hydroxide such as sodium hydroxide or sodium carbonate and a borohydride compound. may also be used.
この工程において、積層板上に吸着させる触媒となりつ
る金属の量を0. 15 mg/dn?以下にすること
により、極端に狭い回路間においても絶縁抵抗の低下は
起らず、わざわざ触媒を除去するという余分な工程が必
要でなくなり、製造工程を簡略化できる0
触媒となりうる金属の量を0. 15 ml?//am
’以下にするためには、触媒となりうる金属イオンを含
む水溶液中の金属イオン濃度を2000〜2500pP
fflの範囲内に管理し、浴の温度を40〜50°C、
積層板の浸漬時間を4〜5分の範囲内に管理すればよい
。In this step, the amount of metal that acts as a catalyst to be adsorbed onto the laminate is reduced to 0. 15 mg/dn? By doing the following, the insulation resistance will not decrease even between extremely narrow circuits, the extra process of removing the catalyst will not be necessary, and the manufacturing process can be simplified. 0. 15ml? //am
'In order to reduce the concentration of metal ions in the aqueous solution containing metal ions that can serve as catalysts to 2000 to 2500 pP,
ffl, and the bath temperature is 40-50°C.
The immersion time of the laminate may be controlled within the range of 4 to 5 minutes.
また、還元液の溶質濃度を0.01〜1 mo I/J
の範囲内、浴の温度を20〜50°Cの範囲内、積層板
の浸漬時間を2〜10分間の範囲内で管理すればよい。In addition, the solute concentration of the reducing solution was adjusted to 0.01 to 1 mo I/J.
The temperature of the bath may be controlled within the range of 20 to 50°C, and the immersion time of the laminate may be controlled within the range of 2 to 10 minutes.
次に、ソルダーレジスト膜を印刷法もしくは光硬化型の
フィルレム状ソ/レダーレジストを用いて、スルーホー
ル部以外をマスクした後、無電解銅めっき浴中に浸漬し
、所望厚みの無電解銅めっき膜を形成させる。これを示
したのが第7図及び第8図である。その他の方法として
、ソルダーレジスト膜のかわりに光硬化型フイルム状レ
ジストでマスクし、無電解銅めっき浴に浸漬し、無電解
銅めっき膜を形成後、ソルダーレジスト膜を形成させて
もよい。Next, the solder resist film is printed using a printing method or a photo-curable fill-em type solder/ruder resist to mask areas other than the through-hole areas, and then immersed in an electroless copper plating bath to coat the solder resist film with a desired thickness. Form a film. This is shown in FIGS. 7 and 8. As another method, instead of the solder resist film, a photocurable film resist may be used as a mask and immersed in an electroless copper plating bath to form an electroless copper plating film, and then a solder resist film may be formed.
無電解銅めっき工程以降は、エツチドフォイル法で用い
られる製造工程と同一の工程を用いてプリント回路板を
製造することができる。例えば、端子部にはニッケルめ
っき、金めつきを施さなければならない。回路全体もし
くはヌル−ホール部に半田が必要な場合、半田めっきを
施すという様に、それぞれ必要な工程を経ることにより
プリント回路板を完成爆せることかできる。After the electroless copper plating step, the printed circuit board can be manufactured using the same manufacturing steps as those used in the etched foil method. For example, terminals must be plated with nickel or gold. If solder is required for the entire circuit or the null-hole area, the printed circuit board can be completed by going through the necessary steps, such as applying solder plating.
以下に実施例を挙げ、本発明をさらに詳細に説明する。The present invention will be explained in more detail with reference to Examples below.
実施例1
ガラスエポキシ鋼張り積層板を用いて、エツチングによ
シ第9図に示す様な、回路を形成した。Example 1 A circuit as shown in FIG. 9 was formed by etching using a glass epoxy steel laminate.
60°Cのシブレイ社製アルキレート溶液に前記積層板
を5分間浸漬して脱脂を行なった。次に30°Cの同社
製コンディショナー1160溶液に8分間浸漬して整面
を行なった。さらに、150fj/l、25°Cの過硫
酸アンモニウム水溶液に2分間浸漬し銅表面をソフトエ
ツチングし1. 8 mol/J 、常温の砒酸水溶液
に1分間浸漬し銅表面のスカムを溶解させた後、触媒付
与を行なった。このとき、吸着させた触媒の量を変化さ
せ、回路間の絶縁抵抗を測定した。この関係を下記の表
に示す。吸着された触媒の量は希硝酸に溶解後、原子吸
光法により定量した。また、絶縁抵抗は100vで、1
分間チャージ後、横河ーヒューレ・・、ト・パ,ンカー
ド社製4829A抵抗計にて測定を行なった。The laminate was degreased by immersing it in an alkylate solution manufactured by Sibley at 60° C. for 5 minutes. Next, the surface was smoothed by immersing it in a conditioner 1160 solution manufactured by the company at 30°C for 8 minutes. Furthermore, the copper surface was soft etched by immersing it in an aqueous ammonium persulfate solution at 150 fj/l and 25°C for 2 minutes. After dissolving the scum on the copper surface by immersing it in an arsenic acid aqueous solution of 8 mol/J at room temperature for 1 minute, a catalyst was applied. At this time, the amount of adsorbed catalyst was varied and the insulation resistance between the circuits was measured. This relationship is shown in the table below. The amount of adsorbed catalyst was determined by atomic absorption spectrometry after dissolving it in dilute nitric acid. Also, the insulation resistance is 100V, 1
After charging for a minute, measurements were made using a 4829A resistance meter manufactured by Yokogawa-Huhle and Topan Card.
表 吸着させた触媒の量と絶縁抵抗との関係実施例2
紙エポキシ銅張シ積層板に金型による打抜きで穴を6け
た。デュポン社製リストン1220を用いて必要な回路
部及びスルーホール部をマスクした。Table: Relationship between amount of adsorbed catalyst and insulation resistance Example 2 Six holes were punched in a paper-epoxy copper-clad laminate using a die. The necessary circuit parts and through-hole parts were masked using DuPont's Riston 1220.
塩化第二銅溶液を用いて余分な@を溶解除去した。Excess @ was dissolved and removed using a cupric chloride solution.
レジストを剥膜後、6[]’Cのシブレイ社製アルキレ
ート溶液に前記積層板を5分間浸漬して脱脂を行なった
。次に、80′Cの同社製コンディショナー1160溶
液に3分間浸漬して整面を行なった。After peeling off the resist, the laminate was immersed in a 6[]'C alkylate solution manufactured by Sibley for 5 minutes to degrease it. Next, the surface was smoothed by immersing it in a conditioner 1160 solution manufactured by the company at 80'C for 3 minutes.
サラVC115oy/g、 25°Cの過硫酸アンモ
ニウムに2分間浸漬し銅表面をソフトエ・ソチングした
。The copper surface was soft etched by immersing it in ammonium persulfate containing 115 oy/g of SaraVC at 25°C for 2 minutes.
1.8mol/ll、常温の硫酸水溶液に1分間浸漬し
銅表面のスカムを溶解させた。金属イオン濃度が200
0ppmで、浴の温度が45℃のPaCe2− SnC
gz−HCeを含む水溶液に5分間浸漬し、さらに各々
0.7 mol/gの硫酸とシュウ酸から成る20°C
の混合液に8分間浸漬し、積層板表面に触媒を吸着させ
た。110℃で10分間乾燥した後、東京応化時のソル
ダーレジストインクを用いてスル−ホール部及びめっき
の被析出部以外の積層板表面にソルダーレジスト膜を形
成させる。It was immersed in a 1.8 mol/ll sulfuric acid aqueous solution at room temperature for 1 minute to dissolve the scum on the copper surface. Metal ion concentration is 200
PaCe2-SnC at 0 ppm and bath temperature of 45 °C
Immersed in an aqueous solution containing gz-HCe for 5 minutes, and then immersed in an aqueous solution containing 0.7 mol/g of sulfuric acid and oxalic acid at 20°C.
The catalyst was immersed in a mixed solution for 8 minutes to adsorb the catalyst on the surface of the laminate. After drying at 110° C. for 10 minutes, a solder resist film is formed on the surface of the laminate other than through-hole areas and areas where plating is to be deposited using a solder resist ink manufactured by Tokyo Ohka.
offf酸銅 0.08 mol/(10ED
TA−ZNa塩 0.05 mol/#0水酸
化ナトリウム 0.20 mol/ItOホルマ
リン 0.20 mol /IIOシア
ン化ナトジナトリウム 5 my/e01.10−フ
ェナントロリン 5 tnII/lOポリエチVング
リコー/I/1 し9上記組成で60°Cの無電解銅
めっき浴に15時間浸漬し、約30μmのめっき膜を形
成させた。めっき膜形成後、絶縁抵抗を測定したが、何
ら異状はなかった。Off-acid copper 0.08 mol/(10ED
TA-ZNa salt 0.05 mol/#0 Sodium hydroxide 0.20 mol/ItO Formalin 0.20 mol/IIO Sodium cyanide 5 my/e01.10-phenanthroline 5 tnII/IO Polyethylene V glycol/I/ 1-9 The above composition was immersed in an electroless copper plating bath at 60°C for 15 hours to form a plating film of about 30 μm. After forming the plating film, insulation resistance was measured, and no abnormality was found.
実施例3
力′ラスエポキシ銅張り積層板にドリルを用いて穴あけ
を行なった。デュポン社製リストン1220を用いて必
要な回路部及びスル−ホール部をマスクした。塩化第二
銅溶液を用いて余分な銅を溶解除去した。レジストを剥
膜後、60°Cのシブレイ社製アルキレート溶液に前記
積層板を5分間浸漬して脱脂を行なった。次に30℃の
同社製コンディショナー1160溶液に3分間浸漬して
整面を行なった。さらに、1.8mol/eの硫酸、2
mol/l=の過酸化水素から成る混合液に2分間浸漬
し銅表面をソフトエツチングした。1.3 mol/I
I 、常温の硫酸水溶液に1分間浸漬し銅表面のスカム
を溶解させた。金属イオン濃度が2500ppmで、浴
の温度が50″CのPt3CM2−5nCe2−NaC
13を含む水溶液に6分間浸漬し、さらに各々0.5
mol/#の硫酸、シュウ酸から成る30°Cの混合液
に8分間浸漬し、積層板表面に触媒を吸着させた。11
0°C110分間乾燥後、東京に化社製のソルダーイン
クを用いてヌル−ホール部及びめっきの被析出部以外の
積層板表面にソルダーレジスト膜を形成させた。実施例
2と同様の無電解銅めっき浴に15時間浸漬し、約30
μmのめっき膜を形成させた。めっき膜形成後、絶縁抵
抗を測定したが、何ら異状はなかった。Example 3 A drill was used to drill holes in a laminate made of epoxy copper. The necessary circuit parts and through-hole parts were masked using DuPont's Riston 1220. Excess copper was dissolved and removed using a cupric chloride solution. After removing the resist, the laminate was immersed in an alkylate solution manufactured by Sibley at 60° C. for 5 minutes to degrease it. Next, the surface was leveled by immersing it in a conditioner 1160 solution manufactured by the company at 30° C. for 3 minutes. Furthermore, 1.8 mol/e of sulfuric acid, 2
The copper surface was soft etched by immersing it in a mixed solution of mol/l hydrogen peroxide for 2 minutes. 1.3 mol/I
I. The scum on the copper surface was dissolved by immersing it in a sulfuric acid aqueous solution at room temperature for 1 minute. Pt3CM2-5nCe2-NaC with a metal ion concentration of 2500 ppm and a bath temperature of 50″C.
13 for 6 minutes, and further immersed in an aqueous solution containing 0.5
The laminate was immersed in a mixed solution of mol/# of sulfuric acid and oxalic acid at 30°C for 8 minutes to adsorb the catalyst on the surface of the laminate. 11
After drying at 0°C for 110 minutes, a solder resist film was formed on the surface of the laminate other than the null-hole areas and the areas where plating was to be deposited, using solder ink manufactured by Kasha in Tokyo. Immersed in the same electroless copper plating bath as in Example 2 for 15 hours,
A plating film of μm was formed. After forming the plating film, insulation resistance was measured, and no abnormality was found.
実施例4
ガラスエポキシ銅張り積層板にドIJ )しを用いて穴
あけを行なった。デュポン社製リストン1220を用い
て必要な回路部及びスルーホール部をマスクした。塩化
第二銅溶液を用いて余分な銅を溶解除去した。レジスト
を剥膜後、40°Cのシエーリング社製クリーナーセキ
ユリガント902ヲ用いて脱脂を行なった。次に1.8
mol/Itの硫酸、2mol/eの過酸化水素から成
る45°Cの混合液に2分間浸漬し銅表面をソフトエツ
チングした。1.8mol/g1常温の硫酸水溶液に1
分間浸漬し銅表面のスカムを溶解させた。金属イオン濃
度が2800ppm、浴の温度が45°Cのパラジウム
有機錯塩化合物を含む水溶液に4分間浸漬し、0.6m
ol/lのポウ水素化合物、0.1 mol//の水酸
化ナトリウムから成る40°Cの混合液K 4分間浸漬
し、積層板表面に触媒を吸着させた。110°C110
分間乾燥後、東京応化社製ソルダーインクを用いてスル
ーホール部及びめっきの被析出部以外の積層板表面にソ
ルダーレジスト膜を形成させた。実施例2と同様の無電
解銅めっき浴に15時間浸漬し、約80μmのめっき膜
を形成させた。めっき膜形成後、絶縁抵抗を測定したが
、何ら異状はなかった。Example 4 Holes were drilled in a glass epoxy copper-clad laminate using a dowel. The necessary circuit parts and through-hole parts were masked using DuPont's Riston 1220. Excess copper was dissolved and removed using a cupric chloride solution. After peeling off the resist, degreasing was performed using a cleaner Sekyuri Gant 902 manufactured by Schering Co., Ltd. at 40°C. Next 1.8
The copper surface was soft etched by immersing it in a 45°C mixed solution consisting of mol/It of sulfuric acid and 2 mol/e of hydrogen peroxide for 2 minutes. 1.8mol/g1 in sulfuric acid aqueous solution at room temperature
It was soaked for a minute to dissolve the scum on the copper surface. A 0.6 m
The plate was immersed for 4 minutes in a mixed solution K at 40°C consisting of ol/l of a porium hydride compound and 0.1 mol/l of sodium hydroxide to adsorb the catalyst on the surface of the laminate. 110°C110
After drying for a minute, a solder resist film was formed on the surface of the laminate other than through-hole areas and areas where plating was to be deposited using solder ink manufactured by Tokyo Ohka Co., Ltd. It was immersed in the same electroless copper plating bath as in Example 2 for 15 hours to form a plating film of about 80 μm. After forming the plating film, insulation resistance was measured, and no abnormality was found.
以上述べた如く、本発明によるプリント回路板の製造方
法は、積層板表面上に吸着させた余分な触媒を除去する
工程を省くことができるので、製造工程が簡略化でき、
吸着させる触媒の量を調節することにより、回路間の絶
縁抵抗の低下を防ぐことができ、また従来法とくらべて
無電解めっきを施す面積が少ないため、製造費が安価と
なるという利点がある。As described above, the method for manufacturing a printed circuit board according to the present invention can omit the step of removing excess catalyst adsorbed on the surface of the laminate, so the manufacturing process can be simplified.
By adjusting the amount of catalyst to be adsorbed, it is possible to prevent a drop in insulation resistance between circuits, and compared to conventional methods, the area covered by electroless plating is smaller, which has the advantage of lower manufacturing costs. .
第1図は本発明の製造方法において使用されるプリント
回路板用の基板の縦断面図、第2図〜第7図は本発明の
製造方法における工程順の製品構成部分の縦断面図であ
る。壕だ、第8図は絶縁抵抗測定用の回路図である。
上記の図面において
1・・・・・・・・・絶縁板
2・・−・・・・・・電解銅箔
3・・・・・・・・−穴
4・・・・・・・・・エツチング用レジスト5・・・・
・・・・・触媒層
6・・・・・・・・・ソルダーレジスト膜7・・・−・
・・・・無電解銅めっき膜特許出願人の名称
イビデン株式会社
代表者 多賀潤一部
〆/l
〆2g
グ3IFIG. 1 is a vertical cross-sectional view of a printed circuit board substrate used in the manufacturing method of the present invention, and FIGS. 2 to 7 are vertical cross-sectional views of product components in the order of steps in the manufacturing method of the present invention. . Figure 8 is a circuit diagram for measuring insulation resistance. In the above drawings, 1... Insulating plate 2... Electrolytic copper foil 3... Hole 4... Etching resist 5...
... Catalyst layer 6 ... Solder resist film 7 ...
...Name of electroless copper plating film patent applicant IBIDEN Co., Ltd. Representative Jun Taga 〆/l 〆2g gu3I
Claims (1)
ルを形成した後、所望回路以外の銅箔をエツチングによ
り溶解除去しスルーホー〃に合わせて回路を形成し、次
いで触媒となりうる金属イオンを金属に還元することの
できる還元液に順次1回ずつ前記積層板を浸漬しこのス
ル−ホール部を含む積層板表面全体に触媒付与を施し、
所望する部分のみ選択的に無電解めっきを施すことによ
り回路を形成するプリント回路板の製造方法において、
触媒付与を施す際、前記触媒となりうる金属イオンを含
む水溶液の金属イオン濃度が2000〜2500 pp
mの範囲内、前記積層板の浸液時間を、4〜6分間の範
囲内に管理し、浴の温度を、40〜50°Cの範囲内と
し、前記還元液の溶質濃度を、0.01〜l molA
の範囲内とし、浴の温度を、20〜50″Cの範囲内と
し、前記積層板の浸漬時間を、2〜10分間の範囲内に
管理することにより前記積層板表面に吸着させる触媒と
力りうる全量の量を0.15 mg、Qnd以下にする
ことを特徴とするプリント回路板の製造方法。 2、前記触媒となりうる金属イオンを含む水溶液は、P
d0g2SnCj!2− HCI (コロイドタイプ)
、Pd(J2SnC#2NaC# (コロイドタイプ)
、ノくラジウム有機錯塩化合物の中から選ばれるいずれ
か1種であることを特徴とする特許請求の範囲第1項記
載の方法。 3、前記還元液は、硝酸・シュウ酸・水酸化ナトリウム
・炭酸ナトリウム及びホウ水素化合物の中から選ばれる
いずれか少なく、とも1種を含む水溶液であることを特
徴とする特許請求の範囲第1項記載の方法。[Claims] 1. After forming through-holes at predetermined positions on the #11 clad laminate, the copper foil other than the desired circuit is dissolved and removed by etching, and a circuit is formed in accordance with the through-hole. The laminate is sequentially immersed once in a reducing solution capable of reducing metal ions that can serve as a catalyst to metal, and the entire surface of the laminate including the through-holes is coated with a catalyst,
In a method for manufacturing a printed circuit board in which a circuit is formed by selectively applying electroless plating only to desired portions,
When applying a catalyst, the metal ion concentration of the aqueous solution containing metal ions that can serve as the catalyst is 2000 to 2500 pp.
The immersion time of the laminated plate was controlled within the range of 4 to 6 minutes, the bath temperature was controlled within the range of 40 to 50°C, and the solute concentration of the reducing solution was controlled within the range of 0. 01~l molA
The temperature of the bath is within the range of 20 to 50''C, and the immersion time of the laminate is controlled within the range of 2 to 10 minutes, thereby increasing the amount of catalyst and force adsorbed onto the surface of the laminate. A method for manufacturing a printed circuit board, characterized in that the total amount that can be used as a catalyst is 0.15 mg, Qnd or less. 2. The aqueous solution containing metal ions that can serve as a catalyst is
d0g2SnCj! 2-HCI (colloid type)
, Pd(J2SnC#2NaC# (colloid type)
2. The method according to claim 1, wherein the radium is any one selected from organic radium complex salt compounds. 3. The reducing solution is an aqueous solution containing at least one selected from nitric acid, oxalic acid, sodium hydroxide, sodium carbonate, and borohydride compounds. The method described in section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4767383A JPS59172796A (en) | 1983-03-22 | 1983-03-22 | Method of producing printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4767383A JPS59172796A (en) | 1983-03-22 | 1983-03-22 | Method of producing printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59172796A true JPS59172796A (en) | 1984-09-29 |
Family
ID=12781784
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4767383A Pending JPS59172796A (en) | 1983-03-22 | 1983-03-22 | Method of producing printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59172796A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04365877A (en) * | 1991-06-13 | 1992-12-17 | Ishihara Chem Co Ltd | Catalyst liquid for copper base material-selecting electroless plating |
JPH04365876A (en) * | 1991-06-13 | 1992-12-17 | Ishihara Chem Co Ltd | Catalyst liquid for copper base selecting electroless plating |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50145856A (en) * | 1974-05-13 | 1975-11-22 | ||
JPS5391381A (en) * | 1977-01-22 | 1978-08-11 | Hitachi Ltd | Method of producing printed circuit board |
JPS5413965A (en) * | 1977-07-01 | 1979-02-01 | Hitachi Ltd | Method of making print wiring substrate |
JPS5516395A (en) * | 1978-07-11 | 1980-02-05 | Westinghouse Electric Corp | Low voltage discharge lamp and method of manufacturing same |
-
1983
- 1983-03-22 JP JP4767383A patent/JPS59172796A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50145856A (en) * | 1974-05-13 | 1975-11-22 | ||
JPS5391381A (en) * | 1977-01-22 | 1978-08-11 | Hitachi Ltd | Method of producing printed circuit board |
JPS5413965A (en) * | 1977-07-01 | 1979-02-01 | Hitachi Ltd | Method of making print wiring substrate |
JPS5516395A (en) * | 1978-07-11 | 1980-02-05 | Westinghouse Electric Corp | Low voltage discharge lamp and method of manufacturing same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04365877A (en) * | 1991-06-13 | 1992-12-17 | Ishihara Chem Co Ltd | Catalyst liquid for copper base material-selecting electroless plating |
JPH04365876A (en) * | 1991-06-13 | 1992-12-17 | Ishihara Chem Co Ltd | Catalyst liquid for copper base selecting electroless plating |
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