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JPH03108793A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH03108793A
JPH03108793A JP24698589A JP24698589A JPH03108793A JP H03108793 A JPH03108793 A JP H03108793A JP 24698589 A JP24698589 A JP 24698589A JP 24698589 A JP24698589 A JP 24698589A JP H03108793 A JPH03108793 A JP H03108793A
Authority
JP
Japan
Prior art keywords
plating
hole
layer
resist film
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24698589A
Other languages
Japanese (ja)
Other versions
JPH0642594B2 (en
Inventor
Masayuki Kawai
雅之 河合
Munehiko Ito
宗彦 伊藤
Hajime Yao
八尾 肇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP1246985A priority Critical patent/JPH0642594B2/en
Publication of JPH03108793A publication Critical patent/JPH03108793A/en
Publication of JPH0642594B2 publication Critical patent/JPH0642594B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To enable plating only in a through-hole part and to improve etching accuracy by restraining dispersion in thickness of metal foil by boring a through- hole after laminating anti-plating resist film on a surface of metallic foil and thereafter by carrying out through-hole plating. CONSTITUTION:An anti-plating resist film 3 is laminated on a surface of an outermost layer metallic foil 2 of a printed wiring board lamination board 1. After a layer of peeling resist 4 is formed as required, a through-hole 5 is bored. Then, it is immersed in salt solution having plating catalysis; a catalyst layer 6 is formed in a part of the through-hole 5; the layer of the peeling resist 4 is peeled to allow the catalyst layer 6 to remain only inside the through-hole 5; catalyst in only a cross section part of the metallic foil 2 is removed by soft etching; and electrolytic plating is carried out to form a plating layer 7 inside the through-hole 5 alone. After plating treatment, the layer of the antiplating resist film 3 is peeled to expose the metallic foil 2.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、プリント配線板の製造方法に関するもので
ある。さらに詳しくは、この発明は、スルポールメツキ
後の金属箔の厚みのバラツキを抑え、エツチング精度を
向」ニさせることのできる新しいプリント配線板の製造
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a printed wiring board. More specifically, the present invention relates to a new method for manufacturing printed wiring boards that can suppress variations in the thickness of metal foil after Sulpol plating and improve etching accuracy.

(従来の技術) 従来より、最外層に金属箔を配設した積層板にスルポー
ル穴あけ加工し、このスルホールをメツキした後に金属
箔のエツチングによって回路形成する方法がプリント配
線板の製造法として広く採用されてきている。
(Prior technology) Conventionally, a method has been widely adopted as a manufacturing method for printed wiring boards, in which a laminate with metal foil arranged on the outermost layer is drilled with through holes, and after the through holes are plated, a circuit is formed by etching the metal foil. It has been done.

しかしながら、近年のプリント配線板の高密度実装への
要求の高まりとともに回路ファインパターン化のための
エツチング精度の向上が強く求められるようになってき
ており、このための新しい方策か必要になってきている
However, as the demand for high-density mounting of printed wiring boards has increased in recent years, there has been a strong demand for improved etching accuracy for fine-patterning circuits, and new measures have become necessary for this purpose. There is.

すなわち、従来の方法においては、スルポールメツキに
ともなって金属箔表面にメツキ層かイ・1@し、このな
め金属箔の厚みのバラツキか避けられず、エツチング精
度の向北には限界があった。
In other words, in the conventional method, a plating layer is formed on the surface of the metal foil due to Sulpol plating, and this unavoidable variation in the thickness of the metal foil has a limit on the etching accuracy. Ta.

このような問題を解決するだめの方法として、たとえば
第2図に示したように、最外層に回路形成用の金属2^
(ア)を有する積層板(イ)をドリル等によって穴あけ
加工し、このスルホール(つ)周囲を除いて金属箔表面
にレジスト(1)を印刷し、次いでスルホールメッキ層
(オ)を形成した後にレジスト(1)を剥離してスルホ
ールメッキにともなう金属箔(ア)の厚みの変化をスル
ホール(つ)周囲に限定することが考えられてもいる。
As a solution to this problem, for example, as shown in Figure 2, a metal 2^ for circuit formation is added to the outermost layer.
After drilling holes in the laminate (B) having (A) using a drill etc., printing resist (1) on the surface of the metal foil except around the through holes (X), and then forming a through hole plating layer (E). It has also been considered to limit the change in the thickness of the metal foil (A) due to through-hole plating to the area around the through-holes by peeling off the resist (1).

(発明が解決しようとする課題) しかしながら、この第2図に示した方策による場合にも
、スルホール(つ)の周囲のメツキ層による盛上りが避
けられず、パターニングに際して支障となり、またレジ
スト印刷時のスルホール(つ)との印刷位置つれの発生
も問題として残されていた。
(Problem to be Solved by the Invention) However, even with the method shown in FIG. 2, the build-up of the plating layer around the through-holes cannot be avoided, which hinders patterning and also causes problems during resist printing. The occurrence of printing position misalignment with the through-holes also remained a problem.

このなめ、これまでの方法によっては、いずれの場合も
金属箔の厚みバラツキを抑え、エツチング精度を向上さ
せるのは離しいのが実情であった。
The reality is that, depending on the methods used so far, it has been difficult to suppress variations in the thickness of metal foil and improve etching accuracy in any case.

この発明は、以上の通りの事情に鑑みてなされたもので
あり、スルホール部のみのメツキを可能とし、金属箔の
厚みのバラツキを抑えてエツチング精度を向上させるこ
とのできるプリン1へ配線板の新しい製造方法を提供す
ることを目的としている。
This invention was made in view of the above-mentioned circumstances, and it is possible to plate only the through-hole portions, suppress variations in the thickness of the metal foil, and improve the etching accuracy of the wiring board. The aim is to provide a new manufacturing method.

(課題を解決するための手段) この発明は、上記の課題を解決するものとして、積層板
最外層の金属箔表面に耐メッキレジストフィルムをラミ
ネー1− した後にスルポール穴あけ加工し、次いでス
ルポールメツキすることを特徴とするプリント配線板の
製造方法を提供する。
(Means for Solving the Problems) This invention solves the above-mentioned problems by laminating a plating-resistant resist film on the surface of the metal foil of the outermost layer of a laminate, followed by Sulpol drilling, and then Sulpol plating. A method for manufacturing a printed wiring board is provided.

また、さらに詳しくは、この発明は、」1記金属箔表面
に耐メツキレシス1〜フイルムをラミネー1−した後に
スルポール穴あけ加工し、キャラリス1〜被覆した後に
スルホールメッキし、次いで耐メンキレジストフィルム
を剥離することからなる方法を提供する。
Further, more specifically, the present invention provides the following method: 1. After laminating the metal foil surface with a scratch-resistant resist film 1, it is subjected to through-hole drilling, and after being coated with a scratch-resistant resist film, through-hole plating is performed, and then a scratch-resistant resist film is applied. A method comprising peeling is provided.

(作 用) この発明の方法においては、耐メツキレシス1〜フイル
ムをラミネー1へした後にスルポール穴あけ加工し、次
いでスルポールメツキするなめ、最外層金属箔表面には
メツキ層は付着ぜす、スルポール周囲にこのメンキ層か
盛」−ることもなく、スルホール部分のみをメツキする
ことができる。
(Function) In the method of the present invention, after the plating resistance film 1 to laminate 1 is formed, Sulpol drilling is performed, and then Sulpol plating is performed. It is possible to plate only the through-hole portions without having to worry about over-filling the peeled layer.

このため、金属箔の厚みのバラツキは抑えられ、ファイ
ンパターン形成のためのエツチング精度は大きく向上す
る。
Therefore, variations in the thickness of the metal foil are suppressed, and the etching accuracy for forming fine patterns is greatly improved.

(実施例) 以下、添付した図面に沿ってこの発明のプリント配線板
の製造方法についてさらに詳しく説明する。
(Example) Hereinafter, the method for manufacturing a printed wiring board of the present invention will be described in more detail with reference to the attached drawings.

第1図は、この発明の方法の工程を示した断面図である
FIG. 1 is a cross-sectional view showing the steps of the method of the present invention.

(a)  t、ず、この第1図に示したように、プリン
ト配線板用積層板(1)の最外層金属箔(2)の表面に
耐メッキレジストフィルム(3)をラミネートする。こ
の時、耐メツキレジストフィルムのラミネートにはパタ
ニングは必要としていない。
(a) As shown in FIG. 1, a plating-resistant resist film (3) is laminated on the surface of the outermost metal foil (2) of the printed wiring board laminate (1). At this time, patterning is not required for laminating the plating-resistant resist film.

積層板(1)としてはプリント配線板用の任意の構成の
ものを使用することができ、金属箔(2)としても、銅
、アルミニウム、その他の金属、合金の適宜な種類の金
属箔が使用される。耐メッキレジストフィルム(3)は
、スルホールメッキ時にメツキ浴に浸漬した場合にも耐
性を有するものとする。具体的には、たとえは日東電工
社製二1〜フロン粘着テープNo、 903 U I−
等の弗素樹脂、ポリイミド樹脂等からなる100μm厚
程度までのフィルムを使用することかできる。
As the laminate (1), any structure for printed wiring boards can be used, and as the metal foil (2), any appropriate type of metal foil such as copper, aluminum, other metals, or alloys can be used. be done. The plating-resistant resist film (3) has resistance even when immersed in a plating bath during through-hole plating. Specifically, an example is Nitto Denko Corporation's 21-Freon adhesive tape No. 903 U I-
A film up to a thickness of about 100 μm made of fluororesin, polyimide resin, etc. can be used.

熱硬化型、光硬化型のレジストフィルムか適宜に使用さ
れる。
A thermosetting resist film or a photocuring resist film is used as appropriate.

(b)  次いで、必要に応じて、この耐メッキレジス
トフィルム(3)層の上に剥離用レジス1〜(4)を配
設する。
(b) Then, if necessary, peeling resists 1 to 4 are provided on the plating-resistant resist film (3) layer.

この時のレジスト(4)はフィルムタイプまたは塗布型
のいずれのものでもよい。
The resist (4) at this time may be either a film type or a coating type.

いずれも次の穴あけ加工時に剥離することのない程度の
付着強度を持つものとし、数10μm〜100μm程度
塗布することとする。
Both should have adhesion strength to the extent that they will not peel off during the next drilling process, and should be coated to a thickness of several tens of micrometers to about 100 micrometers.

たとえば、この剥離用レジスト(4)の塗布型のものと
しては、サンノプコ社製TC−5803N等を50〜8
0 μm程度塗布することかできる。
For example, as a coating type of this peeling resist (4), TC-5803N manufactured by Sannopco Co., Ltd.
It is possible to apply approximately 0 μm.

なお、この工程(b)は省略し、剥離用レジスト(4)
を使用しなくともよい。
Note that this step (b) is omitted and the peeling resist (4)
It is not necessary to use .

(c)  必要に応じてこの剥離用レジスト(4)層を
形成した後に、積層板(1)に対してドリル等によって
スルホール(5)穴あけ加工を行う。この穴あけ加工法
としては、これまでに知られている方法を採用ずれはよ
く、所定の位置にスルホール(5)を形成する。
(c) After forming this peeling resist (4) layer as required, through-holes (5) are drilled in the laminate (1) using a drill or the like. As this drilling method, a method known up to now is used, and a through hole (5) is formed at a predetermined position.

(d、 )  次いで、スルポール(5)穴あけ加工し
た積層板(1)は、メツキ処理のためのキャタリスト塗
布のため、メツキ触媒作用を有する塩溶液に漫潰し、ス
ルホール(5)部にキャタリスト層(6)を形成する。
(d,) Next, the laminate (1) with Sulpol (5) holes drilled therein was soaked in a salt solution having a plating catalytic action to apply a catalyst for plating treatment, and a catalyst was applied to the through holes (5). Form layer (6).

たとえば無電解メツキに際しては、パラジウム等の塩か
らなるキャラリス1〜層(6)を形成する。このための
方法も、従来のものを適宜に採用することができる。
For example, in the case of electroless plating, layers 1 to 6 (layers 6) made of a salt such as palladium are formed. Conventional methods can also be adopted as appropriate for this purpose.

(e)  キャタリスト層(6)を形成した後に、スル
ポール(5)内部にのみキャタリスト層(6)が残るよ
うに、剥離用レジスト〈4)層を剥離する。
(e) After forming the catalyst layer (6), the peeling resist (4) layer is peeled off so that the catalyst layer (6) remains only inside the Surpol (5).

この処理により、耐メツキレジストフィルム(3)層か
露出することになる。
This treatment exposes the plating-resistant resist film (3) layer.

(f)  この状態において、金属箔(2)の断面部の
みのキャタリス1〜をソフトエツチングによって除去し
、次いで電解メツキするか、あるいは、無電解メツキし
た後に電解メツキして、第1図に示したようにスルホー
ル(5)内にのみメツキ層(7)を形成する。
(f) In this state, only the cross section of the metal foil (2) is removed by soft etching and then electrolytically plated, or electroless plated and then electrolytically plated as shown in FIG. As described above, the plating layer (7) is formed only within the through hole (5).

このいずれの方法を採用するかによってキャラリス1〜
層(6)の構成や、処理条件を適宜に選択すればよい。
Depending on which method you use, Characteris 1~
The structure of the layer (6) and the processing conditions may be selected as appropriate.

(g)  メツキ処理後に、耐メッキレジストフィルム
(3)層を剥離して、金属箔〈2)を露出させる。金属
箔(2)とスルポール(5)内のメツキ層(7)とは導
通ずることになる。
(g) After the plating process, the plating-resistant resist film (3) layer is peeled off to expose the metal foil (2). The metal foil (2) and the plating layer (7) in the Surpol (5) are electrically connected.

たとえば以上の工程によって、スルポール(5ン内のみ
のメツキ層(7)形成が可能となり、金属箔(2)表面
でのメツキ処理による厚みバラツキは発生しない。
For example, through the above steps, it is possible to form the plating layer (7) only within the Surpol (5th layer), and no variation in thickness will occur due to the plating process on the surface of the metal foil (2).

第2図は工程(b)を省略した場合を示している。スル
ポール(5)内にのみ必要に応じてキャラリス1〜層(
6)を形成し、メツキ処理するようにしている。
FIG. 2 shows the case where step (b) is omitted. If necessary, apply Charalis 1 to layer (
6) is formed and plated.

もちろん、この発明は、その細部について様々な態様か
可能であり、以上の例示に限られるものではない。
Of course, this invention can be modified in various ways in terms of details, and is not limited to the above-mentioned examples.

(発明の効果) この発明により、以上詳しく説明した通り、両面プリン
ト配線板、多層板等のスルホールのみのメツキか可能と
なり、メツキ処理による金属箔の厚みバラツキは発生せ
ず、高精度エツチングによるパターニングか可能となる
(Effects of the invention) As explained in detail above, this invention makes it possible to plate only through-holes in double-sided printed wiring boards, multilayer boards, etc., eliminates variations in the thickness of metal foil due to plating processing, and allows patterning by high-precision etching. It becomes possible.

【図面の簡単な説明】 第1図および第2図は、各々、この発明の製造法を示し
た工程断面図である。第3図は、従来法の一例を示した
工程断面図である。 1・・・積 層 板 2・・・金 属 箔 3・・・レジストフィルム 4・・・剥離用レジスト 5・・・スルホール 6・・・キャタリスト層 7・・・メツキ層
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 2 are process cross-sectional views showing the manufacturing method of the present invention, respectively. FIG. 3 is a process sectional view showing an example of a conventional method. 1... Laminated plate 2... Metal foil 3... Resist film 4... Peeling resist 5... Through hole 6... Catalyst layer 7... Plating layer

Claims (2)

【特許請求の範囲】[Claims] (1)積層板最外層の金属箔表面に耐メッキレジストフ
ィルムをラミネートした後にスルホール穴あけ加工し、
次いでスルホールメッキすることを特徴とするプリント
配線板の製造方法。
(1) After laminating a plating-resistant resist film on the metal foil surface of the outermost layer of the laminate, through-hole drilling is performed,
A method for manufacturing a printed wiring board, which comprises subsequently performing through-hole plating.
(2)スルホール穴あけ加工した後に、キャタリスト被
覆し、スルホールメッキの後に耐メッキレジストフィル
ムを剥離することからなる請求項(1)記載のプリント
配線板の製造方法。
(2) The method for manufacturing a printed wiring board according to claim (1), which comprises the steps of: coating the catalyst after through-hole drilling, and peeling off the plating-resistant resist film after through-hole plating.
JP1246985A 1989-09-22 1989-09-22 Method for manufacturing printed wiring board Expired - Lifetime JPH0642594B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1246985A JPH0642594B2 (en) 1989-09-22 1989-09-22 Method for manufacturing printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1246985A JPH0642594B2 (en) 1989-09-22 1989-09-22 Method for manufacturing printed wiring board

Publications (2)

Publication Number Publication Date
JPH03108793A true JPH03108793A (en) 1991-05-08
JPH0642594B2 JPH0642594B2 (en) 1994-06-01

Family

ID=17156655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1246985A Expired - Lifetime JPH0642594B2 (en) 1989-09-22 1989-09-22 Method for manufacturing printed wiring board

Country Status (1)

Country Link
JP (1) JPH0642594B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08186373A (en) * 1994-12-28 1996-07-16 Nec Toyama Ltd Manufacture of printed wiring board
JP2006269638A (en) * 2005-03-23 2006-10-05 Sumitomo Bakelite Co Ltd Method for manufacturing circuit board, circuit board and printed circuit board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149091A (en) * 1983-02-16 1984-08-25 松下電器産業株式会社 Both-side printed circuit board and method of producing same
JPH03104089A (en) * 1989-09-18 1991-05-01 Hitachi Ltd semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149091A (en) * 1983-02-16 1984-08-25 松下電器産業株式会社 Both-side printed circuit board and method of producing same
JPH03104089A (en) * 1989-09-18 1991-05-01 Hitachi Ltd semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08186373A (en) * 1994-12-28 1996-07-16 Nec Toyama Ltd Manufacture of printed wiring board
JP2006269638A (en) * 2005-03-23 2006-10-05 Sumitomo Bakelite Co Ltd Method for manufacturing circuit board, circuit board and printed circuit board

Also Published As

Publication number Publication date
JPH0642594B2 (en) 1994-06-01

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