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JPS6155990A - Method of producing printed circuit board - Google Patents

Method of producing printed circuit board

Info

Publication number
JPS6155990A
JPS6155990A JP17768784A JP17768784A JPS6155990A JP S6155990 A JPS6155990 A JP S6155990A JP 17768784 A JP17768784 A JP 17768784A JP 17768784 A JP17768784 A JP 17768784A JP S6155990 A JPS6155990 A JP S6155990A
Authority
JP
Japan
Prior art keywords
copper
catalyst
plating
resist
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17768784A
Other languages
Japanese (ja)
Other versions
JPH0547998B2 (en
Inventor
上山 宏治
神代 健夫
岡村 寿郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP17768784A priority Critical patent/JPS6155990A/en
Publication of JPS6155990A publication Critical patent/JPS6155990A/en
Publication of JPH0547998B2 publication Critical patent/JPH0547998B2/ja
Granted legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は印jli’l配線也の製造法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method of manufacturing a wiring board.

(従来の技術) 印刷配線板の高密度化に伴って、平面回路を銅張積層載
をエツチングして構成するため、平面回路が均一厚みで
あり細線パターンの形成に適するものとして、次の方法
がある。
(Prior art) With the increasing density of printed wiring boards, planar circuits are constructed by etching copper-clad laminates. Therefore, the following method has been developed, assuming that the planar circuits have a uniform thickness and are suitable for forming fine line patterns. There is.

すなわち、触媒入り銅張り積層板の鋼箔上に、エツチン
グレジストを形成し、エツチングを行にめっきレジスト
を印刷し、無電解めっきを穴の内壁およびパッド上のみ
に施して、両面の導通をはかり1両面スルーホール配線
板を作成する方法である。
In other words, an etching resist is formed on the steel foil of the catalyst-containing copper-clad laminate, a plating resist is printed on the etching line, and electroless plating is applied only to the inner walls of the holes and on the pads to ensure continuity on both sides. This is a method for creating a single-sided through-hole wiring board.

この場合、めっきレジスト印刷を行う際、なんらかの原
因で印刷のずれが発生し、その印刷ずれによって、めっ
きレジストの印刷されない触媒入基材表面部分が印刷ず
れの程度によって露出する。その状態で無電解めっき液
に浸漬すると、めっきレジスト印刷のずれによって発生
しためっきレジストの印刷されない触媒入り基材表面の
露出部分にめりきが析出されてしまううその結果バット
の形状がめつきレジスト印刷のずれ方向に拡大され、V
4接パターンとの間隔が狭くなり、印刷配線板の高密度
化の障害となっていた。
In this case, when printing the plating resist, printing misalignment occurs for some reason, and due to the printing misalignment, the surface portion of the catalyst-containing substrate where the plating resist is not printed is exposed depending on the degree of the printing misalignment. If it is immersed in an electroless plating solution in that state, plating will be deposited on the exposed part of the catalyst-containing substrate surface where the plating resist is not printed, which is caused by misalignment of the plating resist printing.As a result, the shape of the bat will change due to the plating resist printing. is expanded in the direction of deviation of V
The distance between the four-contact pattern became narrower, and this became an obstacle to increasing the density of printed wiring boards.

(発明の目的) 本発明の目的は、高密度配線パターンの形成を可能とす
る印刷配線板の製造法を提供するにある。
(Object of the Invention) An object of the present invention is to provide a method for manufacturing a printed wiring board that enables the formation of a high-density wiring pattern.

(発明の構成) 本発明は次のA−Fの工程を含む印刷配線板の製造法で
ある。
(Structure of the Invention) The present invention is a method for manufacturing a printed wiring board including the following steps A to F.

A、触媒入り積層板の表面に触媒を含有しない樹脂層を
設けた捜啼板の表面に銅箔を張り合せた銅張り積層板を
準備する。
A. A copper-clad laminate is prepared by laminating a copper foil on the surface of a probe plate, which has a catalyst-containing resin layer provided on the surface of the catalyst-containing laminate.

B、穴あけを行う。B. Drill a hole.

C,シーディングを行51 D、エツチングを行い、回路以外の不要銅を除去する。C, seeding row 51 D. Perform etching to remove unnecessary copper other than the circuit.

E、めっきレジストを形成する。E. Form a plating resist.

F、無電解鋼めっき液に浸漬する。F. Immerse in electroless steel plating solution.

以下図面に基い℃、本発明を説明する。The present invention will be explained below based on the drawings.

@1図は、触媒入り銅張り積層板であり、1は積層板、
2は銅箔であり5は触媒を含まね樹脂層である。触媒を
含まぬ樹脂層としては、積層板を構成するものと同種の
プリプレグが好ましい。又鋼箔裏面の接着剤層も使用さ
れる。この層の厚みの制限は特にはない。
@1 Figure is a copper-clad laminate containing a catalyst; 1 is a laminate;
2 is a copper foil, and 5 is a resin layer that does not contain a catalyst. Preferably, the catalyst-free resin layer is the same type of prepreg as that constituting the laminate. An adhesive layer on the back side of the steel foil is also used. There are no particular restrictions on the thickness of this layer.

触媒としては、元素周期律表の■族および第18族VC
属する金属、たとえば、ニッケル、金、銀、プラチナ、
パラジウム、ロジウム、銅、イリジウム等、又はこれら
の酸化物、堪化物、臭化物、弗化物、エチルアセテート
、フルオロボレート、硝酸塩、硫酸塩、アセテート等を
挙げることができる。特に有用なのは、パラジウム、金
、プラチナ、銅、塩化パラジウム、塩化金、塩化プラチ
ナ、酸化銅またはこれらと塩化第1錫を組合せたもので
ある。これらの触媒をAj !0B−5i02系の担体
に吸着させ、又、エポキシ樹脂に混合したものをフェス
中に分散させ′″C積層板を作り、触媒入り銅張り積層
板とする。
As a catalyst, group Ⅰ and group 18 VC of the periodic table of elements are used.
metals such as nickel, gold, silver, platinum,
Examples include palladium, rhodium, copper, iridium, etc., or their oxides, fluorides, bromides, fluorides, ethyl acetates, fluoroborates, nitrates, sulfates, acetates, and the like. Particularly useful are palladium, gold, platinum, copper, palladium chloride, gold chloride, platinum chloride, copper oxide or their combinations with stannous chloride. Aj these catalysts! It was adsorbed onto a 0B-5i02 carrier, and mixed with epoxy resin and dispersed in a face to make a ``''C laminate, which was then used as a catalyst-containing copper-clad laminate.

次に第2図に示すように予じめ定められた箇所に穴4が
明けられる。穴明けは、ドリリング、パンチング等で行
なわれる。
Next, as shown in FIG. 2, holes 4 are drilled at predetermined locations. The hole is made by drilling, punching, etc.

次に第5図(示すようにシーディングを行う。Next, seeding is performed as shown in FIG.

シーディングは、触媒処理液(例えばHS −201B
1日立化成工業■製1坏品名)に浸漬することにより行
う、、5はシーダーである。
Seeding is performed using a catalyst treatment liquid (e.g. HS-201B
1. It is carried out by immersing it in Hitachi Chemical Co., Ltd. (product name). 5 is cedar.

次に第4図に示すようにエツチングレジスト6を形成す
る。エツチングレジスト6はシルクスクリーン法で形成
1−てもす(、又、感光性樹脂フィルムを使用し、露光
、現像を行って形成することも出来る。エツチングレジ
スト6は、平面回路となるべき箇所、穴、及び大周辺の
パッドとなるべき箇所に形成する。
Next, as shown in FIG. 4, an etching resist 6 is formed. The etching resist 6 can be formed using a silk screen method (or it can also be formed by using a photosensitive resin film and performing exposure and development. Form the holes and the areas that should become pads around the large periphery.

エツチングレジスト6は、シーディングの前に形成して
も良(、又、穴8Aけの前に形成しても良い。
The etching resist 6 may be formed before seeding (or may be formed before the holes 8A are formed).

次に、第5図に示すようにエツチングを行った後エツチ
ングレジストを除去する。エツチングは、塩化第二鉄溶
液、塩化第二銅溶液、過硫酸アンモニウム溶液、アルカ
リエツチング液等通常のエツチング液が使用される。エ
ツチングを行つた後、エツチングレジストを除去する。
Next, as shown in FIG. 5, after etching is performed, the etching resist is removed. For etching, common etching solutions such as ferric chloride solution, cupric chloride solution, ammonium persulfate solution, and alkaline etching solution are used. After etching, the etching resist is removed.

エツチングレジストの除去は、溶剤による除去、機械的
除去等通常の方法が使用される。
The etching resist can be removed by conventional methods such as solvent removal and mechanical removal.

次に第6図に示すようにめっきレジスト7を形成する。Next, a plating resist 7 is formed as shown in FIG.

めっきレジスト7は、大、及び大周辺のパッドとなるべ
き箇所を除いて形成される。
The plating resist 7 is formed except for the large area and the areas around the large area that should become pads.

めっきレジストは、シルクスクリーン法によっても、又
、感光性樹脂フィルムを使用し、露光、現像を行りて形
成することも出来る。
The plating resist can be formed by a silk screen method or by using a photosensitive resin film, exposing it to light, and developing it.

次に第7図に示すように無電88銅めりき液に浸漬し、
めりきレジストが形成されていない箇所すなわち、大内
壁、パッド部に無電解めっき8を形成する。
Next, as shown in Figure 7, it is immersed in an electroless 88 copper plating solution.
Electroless plating 8 is formed on areas where the plating resist is not formed, that is, on the inner wall and pad portions.

無電解鋼めっき液は、例えば、銅イオンα004〜α2
モル/!、銅イオンの錯化剤αo。
For example, the electroless steel plating solution contains copper ions α004 to α2
Mol/! , a copper ion complexing agent αo.

4〜1モル/l、還元剤0.01〜0.25 モh/l
および田を11.8〜1五5にするに必要な量の…調整
剤、を基本組成とするものが使用される。無電解めつき
は厚み10〜100μm程度形成されろう (発明の効果) 第7図は本発明 得られた印刷配線板の断面図であり、
本発明に於ては、たとえ、めりきレジスト印刷がずれて
基材表面が露出してもその部分はめっきが析出しないた
めめりきレジスト印刷がずれてもパッド部分の形状が変
ったり、隣接の導体部分に接近することなく精度の良い
プリント配線板を作成することができる。
4-1 mole/l, reducing agent 0.01-0.25 moh/l
and an amount of adjusting agent necessary to bring the grain size to 11.8 to 155. Electroless plating will be formed to a thickness of about 10 to 100 μm (effect of the invention) FIG. 7 is a cross-sectional view of a printed wiring board obtained according to the present invention.
In the present invention, even if the plated resist printing is shifted and the base material surface is exposed, the plating will not precipitate on that part, so even if the plated resist printing is shifted, the shape of the pad part will change or the shape of the adjacent pad will not change. It is possible to create a printed wiring board with high precision without getting close to the conductor part.

そのため、めっきレジスト印刷のパターンに対する位置
合せ作業が簡易化される。
Therefore, the alignment work for the plating resist printed pattern is simplified.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第7図は本発明の方法を示す断面図である。 符号の説明 1、触媒入り積層板 2、鋼箔 五 触媒を含まぬ樹脂層 4、穴 5、 シーグー & エツチングレジスト 乙 めっきレジスト & 無電解めっき 1 to 7 are cross-sectional views showing the method of the present invention. Explanation of symbols 1. Laminate plate with catalyst 2. Steel foil 5. Resin layer that does not contain catalyst 4. Hole 5. Seagu & etching resist Otsu plating resist & Electroless plating

Claims (1)

【特許請求の範囲】 1、次の工程を含む印刷配線板の製造法。 A、触媒入り積層板の表面に触媒を含有しない樹脂層を
設けた積層板の表面に銅箔を張 り合せた銅張り積層板を準備する。 B、穴あけを行う。 C、シーディングを行う。 D、エッチングを行い、回路以外の不要銅を除去する。 E、めっきレジストを形成する。 F、無電解銅めっき液に浸漬する。
[Claims] 1. A method for manufacturing a printed wiring board including the following steps. A. A copper-clad laminate is prepared by laminating copper foil on the surface of a laminate containing a catalyst and a resin layer not containing a catalyst provided on the surface of the laminate. B. Drill a hole. C. Perform seeding. D. Perform etching to remove unnecessary copper other than the circuit. E. Form a plating resist. F. Immerse in electroless copper plating solution.
JP17768784A 1984-08-27 1984-08-27 Method of producing printed circuit board Granted JPS6155990A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17768784A JPS6155990A (en) 1984-08-27 1984-08-27 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17768784A JPS6155990A (en) 1984-08-27 1984-08-27 Method of producing printed circuit board

Publications (2)

Publication Number Publication Date
JPS6155990A true JPS6155990A (en) 1986-03-20
JPH0547998B2 JPH0547998B2 (en) 1993-07-20

Family

ID=16035347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17768784A Granted JPS6155990A (en) 1984-08-27 1984-08-27 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS6155990A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56151082A (en) * 1980-04-24 1981-11-21 Brother Ind Ltd Composite type sewing machine
JPS62295487A (en) * 1986-06-16 1987-12-22 株式会社日立製作所 Printed circuit board manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821394A (en) * 1981-07-29 1983-02-08 三喜工業株式会社 Method of producing printed circuit board
JPS5958894A (en) * 1982-09-28 1984-04-04 日立化成工業株式会社 Method of producing through hole circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821394A (en) * 1981-07-29 1983-02-08 三喜工業株式会社 Method of producing printed circuit board
JPS5958894A (en) * 1982-09-28 1984-04-04 日立化成工業株式会社 Method of producing through hole circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56151082A (en) * 1980-04-24 1981-11-21 Brother Ind Ltd Composite type sewing machine
JPS62295487A (en) * 1986-06-16 1987-12-22 株式会社日立製作所 Printed circuit board manufacturing method

Also Published As

Publication number Publication date
JPH0547998B2 (en) 1993-07-20

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