[go: up one dir, main page]

JPH0547998B2 - - Google Patents

Info

Publication number
JPH0547998B2
JPH0547998B2 JP59177687A JP17768784A JPH0547998B2 JP H0547998 B2 JPH0547998 B2 JP H0547998B2 JP 59177687 A JP59177687 A JP 59177687A JP 17768784 A JP17768784 A JP 17768784A JP H0547998 B2 JPH0547998 B2 JP H0547998B2
Authority
JP
Japan
Prior art keywords
electroless plating
hole
catalyst
plating
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59177687A
Other languages
Japanese (ja)
Other versions
JPS6155990A (en
Inventor
Koji Kamyama
Takeo Kamishiro
Toshiro Okamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Lincstech Circuit Co Ltd
Original Assignee
Hitachi AIC Inc
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi AIC Inc, Hitachi Chemical Co Ltd filed Critical Hitachi AIC Inc
Priority to JP17768784A priority Critical patent/JPS6155990A/en
Publication of JPS6155990A publication Critical patent/JPS6155990A/en
Publication of JPH0547998B2 publication Critical patent/JPH0547998B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、印刷配線板の製造方法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for manufacturing a printed wiring board.

(従来の技術) 印刷配線板の高密度化に伴つて、平面回路を銅
張り積層板の不要な銅箔部分をエツチング除去し
て構成するため、平面回路が均一厚みであり、細
線パターンの形成に適するものとして、次の方法
がある。
(Prior art) With the increasing density of printed wiring boards, planar circuits are constructed by removing unnecessary copper foil parts of copper-clad laminates by etching. The following methods are suitable.

すなわち、無電解めつき用触媒入り銅張り積層
板の銅箔上に、エツチングレジストを形成し、回
路導体として不要な箇所の銅箔のエツチング除去
を行なつて、回路パターンを形成し、その回路パ
ターンの接続のためにに必要な箇所に穴を明けた
後、穴内壁及びパツド以外の部分にめつきレジス
トを印刷し、無電解めつきを穴の内壁およびパツ
ド上のみに行なつて、両面の回路の接続を行な
い、両面スルーホール配線板を作成する方法が、
特開昭58−21394号公報に開示されている。
That is, an etching resist is formed on the copper foil of a copper-clad laminate containing a catalyst for electroless plating, and the copper foil is etched away from areas unnecessary as circuit conductors to form a circuit pattern. After drilling holes in the necessary locations for pattern connection, print a plating resist on the inner wall of the hole and areas other than the pad, and perform electroless plating only on the inner wall of the hole and on the pad. The method of connecting the circuits and creating a double-sided through-hole wiring board is as follows.
It is disclosed in Japanese Patent Application Laid-Open No. 58-21394.

(発明が解決しようとする課題) この場合、めつきレジストの印刷を行なう際、
作業誤差等によつて印刷のずれが発生し、その印
刷ずれによつて、めつきレジストの印刷されない
無電解めつき用触媒入り絶縁板の表面部分が露出
する。この状態で無電解めつき液に浸漬すると、
めつきレジストから露出した無電解めつき用触媒
入り絶縁板の表面部分にめつきが析出してしま
う。その結果、パツドの形状がめつきレジスト印
刷のずれた方向に拡大され、隣接する回路パター
ンとの間隔が狭くなり、あるいは配線密度が高い
ときには短絡して、印刷配線板の高密度化の障害
となつていた。
(Problem to be solved by the invention) In this case, when printing the plating resist,
Misalignment of printing occurs due to work errors and the like, and due to the misalignment of printing, the surface portion of the catalyst-containing insulating plate for electroless plating where the plating resist is not printed is exposed. When immersed in electroless plating solution in this state,
Plating is deposited on the surface of the insulating plate containing a catalyst for electroless plating exposed from the plating resist. As a result, the shape of the pad expands in the direction of the plating resist printing, narrowing the gap between adjacent circuit patterns, or short circuiting when the wiring density is high, which becomes an obstacle to increasing the density of printed wiring boards. was.

本発明は、このような課題を解決し、高密度配
線を簡便に行なえる印刷配線板の製造方法を提供
することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a printed wiring board that can solve these problems and easily perform high-density wiring.

(課題を解決するための手段) 本発明の印刷配線板の製造法は、以下の主な工
程からなり、特にめつきレジストの形成作業の簡
易化が図れることを特徴とする。
(Means for Solving the Problems) The method for manufacturing a printed wiring board of the present invention consists of the following main steps, and is characterized in that it can particularly simplify the work of forming a plating resist.

A 無電解めつき用触媒入り絶縁板の表面に前記
無電解めつき用触媒を含まない樹脂層を設けた
積層板の表面に銅箔を貼り合わせた銅張り積層
板を準備する。
A. A copper-clad laminate is prepared by bonding copper foil to the surface of a laminate in which a resin layer not containing the electroless plating catalyst is provided on the surface of an insulating plate containing a catalyst for electroless plating.

B 回路パターンの接続のために必要な箇所に穴
あけを行なう。
B. Drill holes where necessary to connect the circuit pattern.

C 穴内壁を含む全表面に無電解めつき用触媒を
付与する。
C Apply an electroless plating catalyst to the entire surface including the inner wall of the hole.

D 前記銅箔のうち平面回路となるべき箇所及び
穴周辺のパツドとなるべき箇所を除きエツチン
グ除去する。
D. Remove the copper foil by etching, except for the areas that should become planar circuits and the areas that should become pads around the holes.

E 穴内壁及び穴周辺のパツドとなるべき箇所を
除き、めつきレジストを形成する。
E. Form a plating resist except for the inner wall of the hole and the areas around the hole that should become pads.

F 無電解めつき液に浸漬し、穴内壁及び穴周辺
のパツドとなるべき箇所に無電解めつきを形成
する。
F: Immerse in electroless plating solution to form electroless plating on the inner wall of the hole and the areas around the hole that should become pads.

(実施例) 以下、図面に従つて、本発明の実施例を説明す
る。
(Example) Examples of the present invention will be described below with reference to the drawings.

第1図は、無電解めつき用触媒入り絶縁板1の
表面に前記無電解めつき用触媒を含まない樹脂層
3を設けた積層板の表面に銅箔2を貼り合わせた
銅張り積層板である。無電解めつき用触媒を含ま
ない樹脂層3としては、エポキシ系プリプレグで
あるGEA−67(日立化成工業株式会社製、商品
名)等を使用する。
FIG. 1 shows a copper-clad laminate in which a copper foil 2 is bonded to the surface of a laminate in which a resin layer 3 not containing the catalyst for electroless plating is provided on the surface of an insulating plate 1 containing a catalyst for electroless plating. It is. As the resin layer 3 that does not contain a catalyst for electroless plating, an epoxy prepreg such as GEA-67 (manufactured by Hitachi Chemical Co., Ltd., trade name) is used.

無電解めつき用触媒としては、元素周期律表の
族および第B族に属する金属、ニツケル、
金、銀、プラチナ、パラジウム、ロジウム、銅、
イリジウム、又はこれらの酸化物、塩化物、臭化
物、弗化物、エチルアセテート、フルオロポレー
ト、硝酸塩、硫酸塩、アセテートおよびこれらの
混合物から選択することができる。特に有用なの
は、パラジウム、金、プラチナ、銅、塩化パラジ
ウム、塩化金、塩化プラチナ、酸化銅またはこれ
らと塩化第1錫とを組み合わせたものである。こ
れらの無電解めつき用触媒を、A2O3−SiO2
の担体に吸着させ、又、エポキシ樹脂に混合した
ものをワニス中に分散させて絶縁板を作り、その
表面に前記無電解めつき用触媒を含まない樹脂層
3を形成して積層板とする。
Catalysts for electroless plating include metals belonging to groups and group B of the periodic table of elements, nickel,
gold, silver, platinum, palladium, rhodium, copper,
It can be selected from iridium or its oxides, chlorides, bromides, fluorides, ethyl acetates, fluoroporates, nitrates, sulfates, acetates and mixtures thereof. Particularly useful are palladium, gold, platinum, copper, palladium chloride, gold chloride, platinum chloride, copper oxide or their combinations with stannous chloride. These electroless plating catalysts are adsorbed onto an A 2 O 3 -SiO 2 based carrier, and a mixture of epoxy resin and dispersed in varnish is used to make an insulating plate, and the electroless plating is applied to the surface of the insulating plate. A resin layer 3 containing no plating catalyst is formed to form a laminate.

次に第2図に示すように予め回路パターンの接
続のために必要な箇所に穴4を明ける。穴明け
は、ドリリング、パンチング等で行なわれる。
Next, as shown in FIG. 2, holes 4 are drilled in advance at locations necessary for connection of the circuit pattern. The hole is made by drilling, punching, etc.

次に第3図に示すようにシーデイングを行な
う。シーデイングは、無電解めつき用触媒溶液で
あるHS−201B(日立化成工業株式会社製、商品
名)に浸漬することにより行なう。図中5はシー
ダー(無電解めつき用触媒)である。
Next, seeding is performed as shown in FIG. Seeding is performed by immersing in HS-201B (manufactured by Hitachi Chemical Co., Ltd., trade name), which is a catalyst solution for electroless plating. 5 in the figure is a seeder (catalyst for electroless plating).

次に第4図に示すようにエツチングレジスト6
を形成する。エツチングレジスト6はシルクスク
リーン印刷法で形成してもよく、また、感光性樹
脂フイルムを使用し、露光、現像を行なつて形成
することもできる。エツチングレジスト6は、平
面回路となるべき箇所、穴、及び穴周辺のパツド
となるべき箇所に形成する。このエツチングレジ
スト6は、シーデイングの前に形成しても良く、
又、穴明けの前に形成しても良い。
Next, as shown in FIG.
form. The etching resist 6 may be formed by silk screen printing, or may be formed by exposing and developing a photosensitive resin film. Etching resist 6 is formed at locations that are to become planar circuits, holes, and locations that are to become pads around the holes. This etching resist 6 may be formed before seeding,
Alternatively, it may be formed before drilling.

次に、第5図に示すように、銅箔のうち平面回
路となるべき箇所、及び穴周辺のパツドとなるべ
き箇所を除き、エツチング除去を行なつた後、前
記エツチングレジストを除去する。エツチング
は、塩化第二鉄溶液、塩化第二銅溶液、過硫酸ア
ンモニウム溶液、アルカリエツチング液等の通常
のエツチング液が使用される。エツチングレジス
トの除去は、溶剤による除去、機械的除去等通常
の方法が使用される。
Next, as shown in FIG. 5, the copper foil is etched away except for the portions that will become planar circuits and the portions that will become pads around the holes, and then the etching resist is removed. For etching, a conventional etching solution such as a ferric chloride solution, a cupric chloride solution, an ammonium persulfate solution, or an alkaline etching solution is used. The etching resist can be removed by conventional methods such as solvent removal and mechanical removal.

次に第6図に示すようにめつきレジスト7を形
成する。めつきレジスト7は、穴、及び穴周辺の
パツドとなるべき箇所を除いて形成される。めつ
きレジスト7は、シルクスクリーン印刷法によつ
ても、又、感光性樹脂フイルムを使用し、露光、
現像を行なつて形成することもできる。
Next, as shown in FIG. 6, a plating resist 7 is formed. The plating resist 7 is formed except for the holes and the areas around the holes that should become pads. The plating resist 7 can be formed using a silk screen printing method, or by using a photosensitive resin film and exposing it to light.
It can also be formed by performing development.

次に第7図に示すように無電解銅めつき液に浸
漬し、めつきレジストが形成されていない箇所す
なわち、穴内壁及び穴周辺のパツドとなるべき箇
所に無電解めつき8を形成する。
Next, as shown in Fig. 7, it is immersed in an electroless copper plating solution to form electroless plating 8 on areas where no plating resist is formed, that is, areas that should become pads on the inner wall of the hole and around the hole. .

無電解銅めつき液は、銅イオン0.04〜0.2モ
ル/、銅イオンの錯化剤0.004〜1モル/、
還元剤0.01〜0.25モル/およびPHを11.8〜13.5
にするに必要な量のPH調整剤を基本組成とするも
のが使用される。無電解めつきは厚み0.01〜0.1
mm程度形成される。
The electroless copper plating solution contains 0.04 to 0.2 mol/copper ion, 0.004 to 1 mol/copper ion complexing agent,
Reducing agent 0.01-0.25 mol/and PH 11.8-13.5
The basic composition used is one containing the necessary amount of PH adjuster to achieve this. Electroless plating has a thickness of 0.01 to 0.1
Formed about mm.

(発明の効果) 以上に説明したように、銅張り積層板が無電解
めつき用触媒を含まない樹脂層を介在するもので
あることにより、めつきレジスト形成時に印刷が
ずれて該樹脂層が露出したまま残つても、その部
分は無電解めつき用触媒を含んでいないので、無
電解めつき時にめつきが析出されず、パツド部分
の形状が変わつたり、隣接する回路パターンに接
近することなく精度のよい印刷配線板を作成する
ことができる。
(Effects of the Invention) As explained above, since the copper-clad laminate has a resin layer that does not contain an electroless plating catalyst, the printing is misaligned during formation of the plating resist, and the resin layer is Even if it remains exposed, that part does not contain the catalyst for electroless plating, so plating will not be deposited during electroless plating, and the shape of the pad part will change or it will come close to the adjacent circuit pattern. It is possible to create printed wiring boards with high precision without any problems.

そのため、めつきレジスト印刷の回路パターン
に対する位置合わせ作業を簡易化することができ
る。
Therefore, it is possible to simplify the alignment work for the circuit pattern of plating resist printing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第7図は、本発明の一実施例の工程を
説明するための断面図である。 符号の説明、1……無電解めつき用触媒を含む
絶縁板、2……銅箔、3……無電解めつき用触媒
を含まない樹脂層、4……穴、5……シーダ(無
電解めつき用触媒)、6……エツチングレジスト、
7……めつきレジスト、8……無電解めつき。
1 to 7 are cross-sectional views for explaining the steps of an embodiment of the present invention. Explanation of symbols, 1... Insulating plate containing catalyst for electroless plating, 2... Copper foil, 3... Resin layer not containing catalyst for electroless plating, 4... Hole, 5... Seeder (no catalyst for electrolytic plating), 6... etching resist,
7...Plating resist, 8...Electroless plating.

Claims (1)

【特許請求の範囲】 1 以下の主な工程からなり、特にめつきレジス
トの形成作業の簡易化が図れることを特徴とする
印刷配線板の製造法 A 無電解めつき用触媒入り絶縁板の表面に前記
無電解めつき用触媒を含まない樹脂層を設けた
積層板の表面に銅箔を貼り合わせた銅張り積層
板を準備する。 B 回路パターンの接続のために必要な箇所に穴
あけを行なう。 C 穴内壁を含む全表面に無電解めつき用触媒を
付与する。 D 前記銅箔のうち平面回路となるべき箇所及び
穴周辺のパツドとなるべき箇所を除きエツチン
グ除去する。 E 穴内壁及び穴周辺のパツドとなるべき箇所を
除き、めつきレジストを形成する。 F 無電解めつき液に浸漬し、穴内壁及び穴周辺
のパツドとなるべき箇所に無電解めつきを形成
する。
[Claims] 1. Method A for manufacturing a printed wiring board, which comprises the following main steps and is characterized in that it particularly simplifies the work of forming a plating resist. Surface of an insulating board containing a catalyst for electroless plating. A copper-clad laminate is prepared by bonding copper foil to the surface of a laminate provided with a resin layer that does not contain the electroless plating catalyst. B. Drill holes where necessary to connect the circuit pattern. C Apply an electroless plating catalyst to the entire surface including the inner wall of the hole. D. Etch away the copper foil except for the areas that will become planar circuits and the areas that will become pads around the holes. E. Form a plating resist except for the inner wall of the hole and the areas around the hole that should become pads. F: Immerse in electroless plating solution to form electroless plating on the inner wall of the hole and the areas around the hole that should become pads.
JP17768784A 1984-08-27 1984-08-27 Method of producing printed circuit board Granted JPS6155990A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17768784A JPS6155990A (en) 1984-08-27 1984-08-27 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17768784A JPS6155990A (en) 1984-08-27 1984-08-27 Method of producing printed circuit board

Publications (2)

Publication Number Publication Date
JPS6155990A JPS6155990A (en) 1986-03-20
JPH0547998B2 true JPH0547998B2 (en) 1993-07-20

Family

ID=16035347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17768784A Granted JPS6155990A (en) 1984-08-27 1984-08-27 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS6155990A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56151082A (en) * 1980-04-24 1981-11-21 Brother Ind Ltd Composite type sewing machine
JPH0673396B2 (en) * 1986-06-16 1994-09-14 株式会社日立製作所 Method of manufacturing printed circuit board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821394A (en) * 1981-07-29 1983-02-08 三喜工業株式会社 Method of producing printed circuit board
JPS5958894A (en) * 1982-09-28 1984-04-04 日立化成工業株式会社 Method of producing through hole circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821394A (en) * 1981-07-29 1983-02-08 三喜工業株式会社 Method of producing printed circuit board
JPS5958894A (en) * 1982-09-28 1984-04-04 日立化成工業株式会社 Method of producing through hole circuit board

Also Published As

Publication number Publication date
JPS6155990A (en) 1986-03-20

Similar Documents

Publication Publication Date Title
EP0478313B1 (en) A multilayer printed circuit board and manufacturing method therefor
JPH04309290A (en) Manufacture of printed circuit board
JPH09246719A (en) Method for formation of conductive layer of substrate
JPH0710029B2 (en) Method for manufacturing laminated circuit board
WO1988005252A1 (en) Method for the manufacture of multilayer printed circuit boards
JPH0547998B2 (en)
JPH05259639A (en) Manufacture of printed wiring board
JPH08107263A (en) Manufacturing method of printed wiring board
JP2828825B2 (en) Method for manufacturing high-density printed wiring board having blind holes
JPH05259614A (en) Resin filling method for printed wiring board
JP2002185140A (en) Multilayer printed circuit board and method of manufacturing the same
JP3648753B2 (en) Wiring board manufacturing method
JP2622848B2 (en) Manufacturing method of printed wiring board
JPH05283859A (en) Manufacture of printed-circuit board
JPS6155991A (en) Method of producing printed circuit board
JPH03225894A (en) Manufacture of printed wiring board
JPS62156898A (en) Manufacture of through-hole printed wiring board
JPS6155989A (en) Method of producing printed circuit board
JPH0567871A (en) Printed-wiring board and manufacture thereof
JPH03201588A (en) Printed circuit board and manufacture thereof
JPS5846698A (en) Method of producing printed circuit board
JPS63185092A (en) Manufacture of printed circuit board
JPS61252689A (en) Manufacture of printed circuit board
JPH0231494A (en) Manufacture of printed-circuit board
JPS6159891A (en) Method of producing printed circuit board