JPS6155991A - Method of producing printed circuit board - Google Patents
Method of producing printed circuit boardInfo
- Publication number
- JPS6155991A JPS6155991A JP17768884A JP17768884A JPS6155991A JP S6155991 A JPS6155991 A JP S6155991A JP 17768884 A JP17768884 A JP 17768884A JP 17768884 A JP17768884 A JP 17768884A JP S6155991 A JPS6155991 A JP S6155991A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- catalyst
- resist
- plating
- plating resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は印刷配線板の製造法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for manufacturing printed wiring boards.
(従来の技術)
印刷配線板の高密度化に伴って、平面回路を銅張積層板
をエツチングして構成するため、平面回路が均一厚みで
あり細線パターンの形成に適するものとして、次の方法
がある。(Prior art) With the increasing density of printed wiring boards, planar circuits are constructed by etching copper-clad laminates. Therefore, the following method has been developed, assuming that the planar circuits have a uniform thickness and are suitable for forming fine line patterns. There is.
すなわち、触媒入r)銅張り積層板のt@箔上に、エツ
チングレジストを形成し、エツチングを行りて、鋼箔の
パターンを形成し、そのパターンの所要の位置に穴を明
けた後パッド以外の部分にめっきレジストを印刷し、無
電解めっきを穴の内壁およびパッド上のみ罠施して、両
面の導通をはかり、両面スルーホール配線板を作成する
方法である。That is, an etching resist is formed on the foil of the catalyst-containing r) copper-clad laminate, etching is performed to form a pattern of steel foil, holes are made in the required positions of the pattern, and then the pad is removed. This is a method to create a double-sided through-hole wiring board by printing a plating resist on the other parts and applying electroless plating only on the inner wall of the hole and on the pad to ensure conduction on both sides.
この場合、めっきレジスト印刷を行う際、なんらかの原
因で印刷のずれが発生し、その印刷ずれによって、めっ
きレジストの印刷されない触媒入基材表面部分が印刷ず
れの程度によって露出する。その状態で無電解めっき液
に浸11jtすると、めっきレジスト印刷のずれによっ
て発生しためっきレジストの印刷されない触媒入り基材
表面の露出部分にめっきが析出さ九てしま5.。In this case, when printing the plating resist, printing misalignment occurs for some reason, and due to the printing misalignment, the surface portion of the catalyst-containing substrate where the plating resist is not printed is exposed depending on the degree of the printing misalignment. If it is immersed in an electroless plating solution in this state for 11 hours, plating will be deposited on the exposed part of the catalyst-containing substrate surface where the plating resist is not printed, which is caused by the misalignment of the plating resist printing.5. .
その結果パッドの形状がめつきレジスト印刷のずれ方向
に拡大され、隣接パターンとの間隔が狭くなり、印刷配
−板の間密度化の障害となっていた。As a result, the shape of the pad is enlarged in the direction of displacement of the plating resist printing, and the distance between adjacent patterns becomes narrower, which becomes an obstacle to increasing the density between the printed wiring boards.
(発明の目的)
本発明の目的は、高密度配線パターンの形成を可能とす
る印刷配線板の製造法を提供するにある。(Object of the Invention) An object of the present invention is to provide a method for manufacturing a printed wiring board that enables the formation of a high-density wiring pattern.
(発明の構成) 本発明は、 A、触媒入り銅張り積層機を準備する。(Structure of the invention) The present invention A. Prepare a copper-clad laminating machine containing a catalyst.
B、エツチングレジストを形成してエツチングする工程
、大明けする工程、めりきレジストを形成する工程を適
宜とることにより、必要な平面回路パターン、必要な箇
所への穴、及び穴部、パッド部を除いた箇所に形成され
ためつぎレジストを有す基板を得る、
C0無電解鋼めりき液に浸漬する、
工程を含む印刷配線板の製造法に於て、触媒入り積層機
の表面に触媒を含有しない樹脂層を設けることを特徴と
するものである。B. By appropriately performing the steps of forming and etching an etching resist, clearing, and forming a plating resist, the necessary planar circuit pattern, holes in the necessary locations, and the hole and pad portions are formed. In a printed wiring board manufacturing method that includes the steps of obtaining a substrate with a resist formed in the removed areas and immersing it in a C0 electroless steel plating solution, a catalyst is contained on the surface of a catalyst-containing laminating machine. The invention is characterized by providing a resin layer that does not contain any resin.
以下図面VC基いて本発明を説明する。The present invention will be explained below with reference to drawing VC.
第1図は、触媒入り銅張り積層板で、1は触媒入り積層
板、2は銅箔であり、3は触媒を含まぬ樹脂層である。FIG. 1 shows a catalyst-containing copper-clad laminate, where 1 is a catalyst-containing laminate, 2 is a copper foil, and 3 is a resin layer that does not contain a catalyst.
触媒を含まぬ樹脂としては、うすい(例えば(LO51
1111程度の)プリプレグ、鋼箔裏面の接着剤(厚さ
αO05〜αQ5mm)のものが使用される。この層が
あまり厚くなると(例えば100μm以上)後工程のス
ルホールめっきに於てめっきが付かない場合がある。As a resin that does not contain a catalyst, thin (for example (LO51)
Prepreg (about 1111) and adhesive on the back side of steel foil (thickness αO 05 to αQ 5 mm) are used. If this layer is too thick (for example, 100 μm or more), it may not be plated in the subsequent through-hole plating process.
触媒としては、元素周期律表の第■族および第1BtI
F:に属する金属、たとえば、二yケル、化物、弗化物
、エチルアセテート、フルオロボレート、硝酸塩、硫酸
塩、アセテート等を挙げることができる。特に有用なの
は、パラジウム、金、プラチナ、銅、塩化パラジウム、
塩化金、塩化プラチナ、酸化鋼またはこれらと塩化第1
錫を組合せたものである。これらの触媒をAhCh51
(h系の担体に吸着させ、又、エポキシ樹脂に混合した
ものをフェス中に分散させて積層板を作り、触媒入り銅
張り積層板とする。As a catalyst, group Ⅰ and 1st BtI of the periodic table of elements are used.
Examples of metals belonging to F: include dichelics, compounds, fluorides, ethyl acetates, fluoroborates, nitrates, sulfates, and acetates. Particularly useful are palladium, gold, platinum, copper, palladium chloride,
Gold chloride, platinum chloride, oxidized steel or these and primary chloride
It is a combination of tin. These catalysts were used as AhCh51
(It is adsorbed onto a h-based carrier, and mixed with epoxy resin and dispersed in a face to make a laminate, and a catalyst-containing copper-clad laminate is made.
次に@2図に示すように予じめ定められた箇所に穴4が
明けられる。穴明けは、ドリリング、パンチング等で行
なわれる。Next, as shown in Figure @2, holes 4 are drilled at predetermined locations. The hole is made by drilling, punching, etc.
次に第5図に示すようにエツチングレジスト5を形成す
る。エツチングレジスト5はシルクスクリーン法で形成
しても良く、又、感光性樹脂フィルムを使用し、露光、
現像を行って形成することも出来る。エツチングレジス
ト5は、平面回路となるべき箇所、穴、及び穴周辺のパ
ッドとなるべき箇所に形成する。Next, as shown in FIG. 5, an etching resist 5 is formed. The etching resist 5 may be formed by a silk screen method, or may be formed by using a photosensitive resin film and exposing to light.
It can also be formed by developing. Etching resist 5 is formed at locations where planar circuits are to be formed, holes, and locations where pads are to be formed around the holes.
次に、W、4図に示すように、エツチングを行りた後エ
ツチングレジストを除去する。エツチングは、塩化第二
鉄溶液、塩化第二M4溶液、過硫酸アンモニウム溶液、
アルカリエツチング液等通庸のエツチング液が使用され
る。エツチングを行い回路以外の不要銅除去した後、エ
ツチングレジストを除去する。エツチングレジストの除
去は、溶剤による除去、機械的除去等通常の方法が使用
される。Next, as shown in FIG. 4, etching is performed and the etching resist is removed. For etching, ferric chloride solution, ferric chloride M4 solution, ammonium persulfate solution,
A common etching solution such as an alkaline etching solution is used. After etching is performed to remove unnecessary copper other than the circuit, the etching resist is removed. The etching resist can be removed by conventional methods such as solvent removal and mechanical removal.
次に第5図に示すようにめりきレジスト6を形成する。Next, as shown in FIG. 5, a plated resist 6 is formed.
めっきレジスト6は、穴、及び穴周辺のパッドとなるべ
き箇所を除い℃形成される。The plating resist 6 is formed at 0.degree. C. except for the holes and the areas around the holes that are to become pads.
めっきレジストは、シルクスクリーン法によっても、又
、感光性樹脂フィルムを使用し、露光、現像を行つて形
成することも出来る。The plating resist can be formed by a silk screen method or by using a photosensitive resin film, exposing it to light, and developing it.
次に第6図に示すように無1を解銅めっき液に浸漬し、
めっきレジストが形成されていない箇所すなわち、穴内
壁、パッド部に無’tx、ysめっき7を形成する。Next, as shown in FIG.
Non'tx, ys plating 7 is formed on areas where the plating resist is not formed, that is, on the inner wall of the hole and on the pad portion.
無電解鋼めっき液は、例えば鋼イオンa、004〜(1
2モル/7I、柑イオンの錯化剤0.004〜1そル/
1.還元剤001〜[L25モル/lおよび川を11.
8〜1五5tlC−fるに必要な量のFl+調整剤、を
基本組成とするものが使用される。The electroless steel plating solution is, for example, steel ion a, 004 to (1
2 mol/7I, citrus ion complexing agent 0.004-1 mol/
1. Reducing agent 001~[L25 mol/l and river 11.
The basic composition used is Fl + regulator in an amount necessary to produce 8 to 155 tlC-f.
無電解めっきは厚み10〜100μm程度形成される。Electroless plating is formed to a thickness of about 10 to 100 μm.
以上は本発明の一例で、B工程として穴明け→エツチン
グ→めっきレジスト形成の工程をとっているが、この他
、エツチング→穴あけ→めっきレジスト形成、エツチン
グ→めっきレジスト形成→穴あけの工程をとることも出
来る。The above is an example of the present invention, and the B process includes the steps of drilling → etching → forming a plating resist. In addition, the steps of etching → drilling → forming a plating resist and etching → forming a plating resist → drilling may also be performed. You can also do it.
(発明の効果)
第6図は本発明により得られた印刷配線板の断面図であ
り、本発明に於ては、たとえ、めっきレジスト形成がず
れて基材表面が4出してもその部分はめっきが析出しな
いためめっきレジスト形成がずれてもパッド部分の形状
が変ったり、隣接の導体部分に接近することなく精度の
良いプリント配線板を作成することができる。(Effects of the Invention) FIG. 6 is a cross-sectional view of a printed wiring board obtained according to the present invention. Since the plating does not precipitate, even if the plating resist is misaligned, the shape of the pad portion will not change or the pad portion will not come close to the adjacent conductor portion, making it possible to create a highly accurate printed wiring board.
そのためめっきレジスト形成のパターンに対する位置合
せ作業が1m易化される。Therefore, the alignment work for the plating resist pattern can be simplified by 1 m.
第1図〜第6図は本発明の方法を示す断面図である。 符号の説明 1、 触媒入り積#機 2、鋼箔 五 触Wを含′士ぬ樹脂層 4、穴 5、 エツチングレジスト & めっきレジスト 乙 無′?!解銅めっき 1 to 6 are cross-sectional views showing the method of the present invention. Explanation of symbols 1. Catalyst loaded # machine 2. Steel foil 5. Resin layer containing no contact W 4. Hole 5. Etching resist & Plating resist Otsu Mu′? ! Copper plating
Claims (1)
ングレジストを形成してエッチングする工程、穴明けす
る工程、めっきレジ ストを形成する工程を適宜とることにより、必要な平面
回路パターン、必要な箇所への 穴、及び穴部、パッド部を除た箇所に形成 されためっきレジストを有す基板を得る、 C、無電解銅めっき液に浸漬する、 工程を含む印刷配線板の製造法に於て、触媒入り積層板
の表面に触媒を含有しない樹脂層を設けることを特徴と
する印刷配線板の製造法。[Claims] 1. A. Preparing a catalyst-containing copper-clad laminate, B. Forming an etching resist and etching, drilling, and forming a plating resist as appropriate. Printing that includes the steps of: obtaining a board having a planar circuit pattern, holes in necessary locations, and plating resist formed in locations other than the holes and pads; C. immersion in an electroless copper plating solution; A method for manufacturing a printed wiring board, which comprises providing a resin layer that does not contain a catalyst on the surface of a catalyst-containing laminate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17768884A JPS6155991A (en) | 1984-08-27 | 1984-08-27 | Method of producing printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17768884A JPS6155991A (en) | 1984-08-27 | 1984-08-27 | Method of producing printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6155991A true JPS6155991A (en) | 1986-03-20 |
Family
ID=16035365
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17768884A Pending JPS6155991A (en) | 1984-08-27 | 1984-08-27 | Method of producing printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6155991A (en) |
-
1984
- 1984-08-27 JP JP17768884A patent/JPS6155991A/en active Pending
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