JPS62232994A - Manufacture of printed circuit board - Google Patents
Manufacture of printed circuit boardInfo
- Publication number
- JPS62232994A JPS62232994A JP7590886A JP7590886A JPS62232994A JP S62232994 A JPS62232994 A JP S62232994A JP 7590886 A JP7590886 A JP 7590886A JP 7590886 A JP7590886 A JP 7590886A JP S62232994 A JPS62232994 A JP S62232994A
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit board
- copper
- plating
- catalyst
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 21
- 239000003054 catalyst Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 239000011889 copper foil Substances 0.000 claims description 10
- 238000007772 electroless plating Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 4
- 238000005553 drilling Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims description 2
- 238000007747 plating Methods 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- 239000000243 solution Substances 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 2
- DHMQDGOQFOQNFH-UHFFFAOYSA-N Glycine Chemical compound NCC(O)=O DHMQDGOQFOQNFH-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 1
- 239000004471 Glycine Substances 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 239000002202 Polyethylene glycol Substances 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920001223 polyethylene glycol Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔並業上の利用分野〕
本発明は、銅張り積層板を用いて、スルーホールなどの
必要な部分のみに選択的に無電解めっきを析出させる経
済的かつ作業性に優れたプリント回路板の製造方法に関
する。[Detailed Description of the Invention] [Field of Application in the Ordinary Industry] The present invention provides an economical and workable method for selectively depositing electroless plating only on necessary areas such as through holes using a copper-clad laminate. The present invention relates to a method of manufacturing a printed circuit board with excellent performance.
従来、プリント回路板の製造方法の主流はエツチドフォ
イル法が一般である。Conventionally, the mainstream method for manufacturing printed circuit boards has been the etched foil method.
例えば、第2図(a)〜(e)に示す様に(1)サブト
ラクティブ法つまシ銅張シ積層板にスルーホールを施し
、余分な銅をエツチングによシ溶解除去し、ソルダーレ
ジスト膜を形成して得られるプリント回路板が良く知ら
れている。For example, as shown in Figures 2(a) to (e), (1) through-holes are made in a subtractive copper-clad laminate, excess copper is dissolved and removed by etching, and a solder resist film is formed. A printed circuit board obtained by forming a wafer is well known.
また(2)特公昭58−6319号の発明では穴壁面及
び銅箔面上に触媒層を形成した積層板の不必要部の銅箔
を溶解除去した後に1穴壁面及び必要回路部に無電解め
っき膜を形成することによシ、スルーホールプリント板
を製造する方法が提案されている。(2) In the invention of Japanese Patent Publication No. 58-6319, after dissolving and removing unnecessary copper foil of a laminated board in which a catalyst layer is formed on the hole wall surface and the copper foil surface, electroless A method of manufacturing a through-hole printed board by forming a plating film has been proposed.
しかし、従来の(1)の方法では溶解除去する銅の量が
多く又、工程も複雑である。そこで、合理的な方法とし
て(2)の方法が考えられるが、無電解めっき処理工程
において鋼箔回路上のめっきの付きまわりが悪い傾向が
あった。特にスルーホールと連結しない微小回路部等に
、無電解めっきの不析出現象が多々みられた。However, in the conventional method (1), a large amount of copper is dissolved and removed, and the process is complicated. Therefore, method (2) can be considered as a rational method, but the plating coverage on the steel foil circuit tends to be poor in the electroless plating process. In particular, non-precipitation phenomena of electroless plating were often observed in microcircuit parts that are not connected to through holes.
本発明は、めっきの必要な部分のみ触媒を施しまためっ
き付きまわシの良いプリント回路板を製造することを目
的としている。The object of the present invention is to manufacture a printed circuit board with good plating coverage in which a catalyst is applied only to the portions that require plating.
上記問題点を解決するため、本発明のプリント回路板の
製造方法は以下のa)〜e)の各工程a)両面銅張り積
層板の所定位置にスルーホール穴明けをする工程
b)スルーホール穴内部を触媒処理する工程C)エツチ
ングで所望のパターンを形成する工程
d)必要部分以外をレジストでマスキングする工程
e)スルーホール穴内部及び所望のパターン部のみ選択
的に無電解めっきをする工程
を順次含むプリント回路板の製造方法において工程b)
とC)の間に銅箔表面に無電解めっき触媒を付与する工
程を含むことを特徴とする。In order to solve the above problems, the method for manufacturing a printed circuit board of the present invention includes the following steps a) to e): a) step of drilling through holes at predetermined positions in a double-sided copper-clad laminate; b) through-holes. Step of catalytically treating the inside of the hole C) Step of forming the desired pattern by etching d) Step of masking the non-necessary portions with resist e) Step of selectively electroless plating only the inside of the through-hole and the desired pattern portion Step b) in a printed circuit board manufacturing method sequentially comprising
It is characterized by including a step of applying an electroless plating catalyst to the surface of the copper foil between and C).
尚、本発明にあたって用いられる積層板は市販されてい
るものすべて使用可能である。今回は、ガラスエポキシ
銅張シ積層板を用いた。また銅箔の厚みも一般に入手可
能な18,56.70μmいずれも使用可能であるが、
高密度回路間隔を形成する上で適切な18μmを使用し
た。次に穴明けの方法としては、ドリル及び金型による
打抜きが考えられるが、本発明に於いては均一なスルー
ホールを形成する上でドリルによる穴明けを行った。ま
た、銅箔上に無電解めっき触媒を付与する方法としては
、ワールドメタル社製AT−80液、日本カニゼン製レ
ッドシューマーなど周知のめつき触媒処理液による処理
があげられる。Note that all commercially available laminates can be used in the present invention. This time, we used a glass epoxy copper-clad laminate. In addition, the thickness of the copper foil can be either 18 or 56.70 μm, which are commonly available.
18 μm was used as it is suitable for forming high density circuit spacing. Next, as a method for making holes, punching using a drill and a die can be considered, but in the present invention, holes were made using a drill to form uniform through holes. Further, as a method of applying an electroless plating catalyst to the copper foil, treatment with a well-known plating catalyst treatment solution such as AT-80 solution manufactured by World Metal Co., Ltd. or Red Schumer manufactured by Nippon Kanigen Co., Ltd. can be mentioned.
以下に本発明の実施例を図面にもとづいて説明する。 Embodiments of the present invention will be described below based on the drawings.
実施例1
第1図(、a)〜(e)は、本発明を工程順に示したも
のである。同IE4(a)は、銅箔2の厚みが18μm
のガラス・エポキシ銅張り積層板1を示す。上記積層板
に同図(b)の様に、回路として必要な部品挿入用、並
びに表裏導通用の穴3をドリルによってあけた。次に6
0℃のディプソール、3%溶液に前記積層板を5分浸漬
して脱脂を行った。さらに、20011/1%常温の過
硫酸アンモニウム水溶液に3分間浸漬し銅表面をソフト
エツチングし、5%、常温硫酸に2分間浸漬し銅表面の
スカムを溶解させた後、穴3に銅めつき膜を形成する事
を目的として、20%%MCIに1分間プレディップし
た後、60 c c / l s常温の日立化成工業社
製H8101B水溶液に10分間浸漬し、積層板表面に
触媒4を吸着させた後、シブレイ社製アクセレレータ−
19で、20℃、6分間活性化処理した。次に、同図(
C)の様に60℃のワールドメタル社製AT−80に5
分間浸漬させ、銅箔上に触媒Wt5を形成した。次にエ
ツチング用レジストとして、アルカリ可溶タイプの光硬
化型フイルム状レジストをラミ不一トシ、露光、現像し
50℃、40″′Be°の塩化第2鉄溶iを用いて、余
分な銅を溶解除去しレジストを剥離することによりバタ
ーニングを行った。そして同図(d)に示す様に、太陽
インキ社製ソルダーインクS−221用いてスルーホー
ル部及びめっきの被析出部以外の積層板表面にンルダー
レジスト膜6を形成させた。Example 1 Figures 1 (a) to (e) show the present invention in the order of steps. In the same IE4(a), the thickness of the copper foil 2 is 18 μm.
A glass-epoxy copper-clad laminate 1 is shown. Holes 3 for inserting components necessary for the circuit and for conducting between the front and back sides were drilled in the laminate as shown in FIG. 2(b). Next 6
The laminate was immersed in a 3% Dipsol solution at 0° C. for 5 minutes to degrease it. Furthermore, the copper surface was soft etched by immersing it in 20011/1% ammonium persulfate aqueous solution at room temperature for 3 minutes, and after immersing it in 5% sulfuric acid at room temperature for 2 minutes to dissolve the scum on the copper surface, hole 3 was filled with copper plating film. After pre-dipping in 20% MCI for 1 minute, it was immersed in a 60 c c / l s H8101B aqueous solution manufactured by Hitachi Chemical Co., Ltd. at room temperature for 10 minutes to adsorb catalyst 4 on the surface of the laminate. After that, use the Sibley accelerator.
Activation treatment was performed at 20° C. for 6 minutes at 19°C. Next, the same figure (
5 in AT-80 made by World Metal Co., Ltd. at 60℃ as shown in C).
The copper foil was immersed for a minute to form a catalyst Wt5 on the copper foil. Next, as an etching resist, an alkali-soluble photocurable film resist was laminated, exposed and developed, and excess copper was removed using ferric chloride solution at 50°C and 40'''Be°. Buttering was performed by dissolving and removing the resist and peeling off the resist.Then, as shown in the same figure (d), using Taiyo Ink Co., Ltd. solder ink S-221, the laminated layers other than the through-hole area and the area where the plating was deposited were removed. A resist film 6 was formed on the surface of the plate.
・硫酸銅 10/l/10EDTA壷
2Na 30fl/10ホルマリン(67%)
5 m4 / l・α、α1−ビピリジル
5ml/AOポリエチレングリコール Q、5/l
/1・グリシン 6 g/l・PH=
12.0 (NaOHで調整)上記組成で72℃の無
電解鋼めっき浴に5時間浸漬し、同図(e)の株に約1
8μmの無電解銅めっき膜7を形成した。・Copper sulfate 10/l/10 EDTA jar 2Na 30 fl/10 formalin (67%)
5 m4 / l・α, α1-bipyridyl
5ml/AO polyethylene glycol Q, 5/l
/1・Glycine 6 g/l・PH=
12.0 (Adjusted with NaOH) The above composition was immersed in an electroless steel plating bath at 72°C for 5 hours, and the strain shown in Figure (e) was coated with about 1
An electroless copper plating film 7 of 8 μm was formed.
この時、銅めつきの付きまわりは良好で独立した微小回
路部にも選択性良く銅めっきは析出し、又めつきふくれ
もなかった。At this time, the coverage of the copper plating was good, the copper plating was deposited with good selectivity even on the independent microcircuit parts, and there was no plating blistering.
実施例2〜8 比較例1
前記実施例1において* A T −80による触媒層
5の形成条件を変更したところ、下記表の様になった。Examples 2 to 8 Comparative Example 1 When the conditions for forming the catalyst layer 5 using *AT-80 in Example 1 were changed, the results were as shown in the table below.
表 AT−80の処理温度、時間による付きまわうとめ
つきふくれの有無の関係
〔発明の効果〕
本発明のプリント回路板の製造方法は以上説明した様に
、銅箔表面に無電解めっき触媒を付与することにより、
銅めつき付きまわりが良く、密着の良いプリント回路板
を得ることができた。Table 1 Relationship between AT-80 treatment temperature and time and the presence or absence of plating and blistering [Effects of the invention] As explained above, the method for producing a printed circuit board of the present invention involves applying an electroless plating catalyst to the surface of the copper foil. By doing so,
A printed circuit board with good copper plating and good adhesion was obtained.
第1図(a)〜(e)は本発明の製造方法における製品
構成部分の縦断面図を工程順に示したものである。また
第2図(a)〜(、e)は、従来法における工程順の製
品構成部分の縦断面図である。
上記の図面において
1・・・・・・絶縁積層板
2・・・・・・電解鋼箔
3・・・・・・穴
4・・・・・・触媒層1
5・・・・・・触媒層2
6・・・・・・ソルダーレジスト膜
7・・・・・・無電解銅めっき膜
以上
サンリツ工業株式会社
m
(α)
<a)
窩 1 図
、 、2
(α)
(Cン
渇 2 図FIGS. 1(a) to 1(e) are longitudinal cross-sectional views of product constituent parts in the manufacturing method of the present invention, shown in the order of steps. Moreover, FIGS. 2(a) to 2(e) are longitudinal cross-sectional views of product constituent parts in the order of steps in the conventional method. In the above drawings, 1... Insulating laminate 2... Electrolytic steel foil 3... Hole 4... Catalyst layer 1 5... Catalyst Layer 2 6...Solder resist film 7...More than electroless copper plating film Sanritsu Industries Co., Ltd. figure
Claims (1)
をする工程 b)スルーホール穴内部を触媒処理する工程c)エッチ
ングで所望のパターンを形成する工程 d)必要部分以外をレジストでマスキングする工程 e)スルーホール穴内部及び所望のパターン部のみ選択
的に無電解めつきをする工程 を順次含むプリント回路板の製造方法において、工程b
)とc)の間に銅箔表面に無電解めつき触媒を付与する
工程を含むことを特徴とするプリント回路板の製造方法
。[Claims] Each of the following steps a) to e) a) Step of drilling through-holes at predetermined positions in a double-sided copper-clad laminate b) Step of treating the inside of the through-hole with a catalyst c) Etching as desired A method for manufacturing a printed circuit board, which sequentially includes the following steps: d) masking non-required portions with a resist; e) selectively electroless plating only the inside of the through-hole and the desired pattern portion; Process b
A method for manufacturing a printed circuit board, comprising the step of applying an electroless plating catalyst to the surface of the copper foil between steps of ) and c).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7590886A JPS62232994A (en) | 1986-04-02 | 1986-04-02 | Manufacture of printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7590886A JPS62232994A (en) | 1986-04-02 | 1986-04-02 | Manufacture of printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62232994A true JPS62232994A (en) | 1987-10-13 |
Family
ID=13589905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7590886A Pending JPS62232994A (en) | 1986-04-02 | 1986-04-02 | Manufacture of printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62232994A (en) |
-
1986
- 1986-04-02 JP JP7590886A patent/JPS62232994A/en active Pending
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