JPS59103348A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To enable efficient gettering by bumping discharging plasma of predetermined gas of halogen group against selective parts except an element forming region to form crystal faults in high density. CONSTITUTION:A wafer is cleansed enough and is purified by removing residual organic substance or heavy metals on its surface. Next, the wafer is put in the plasma of CXyY4-y gas (e.g. CF4, CF3Br) wherein X and Y are halogen elements and y<4, and plurality of crystal faults are introduced into selective parts of the wafer. By heat treatment following that, heavy metals or minute faults inside the wafer are gathered and gettering brings its effect. This method enables to do gettering in much cleaner condition than that in the conventional methods as well as to do gettering during an arbitrary process of the manufacture. In addition, the gettering is made on the same plane as an element forming plane so that plurality of wafers arranged in order can be subjected to gettering, resulting in high efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to an improvement in the process of introducing crystal defects during catering.

2. Description of the Related Art In recent years, there has been a growing demand for semiconductor devices with a large area and a high degree of integration. For example, it is a CCI) image sensor. In order to realize such a device, it is necessary to prevent crystal defects from existing within the device region. The presence of crystal defects causes a leakage current in the device, and in severe cases, it makes the device inoperable. However, during the manufacturing process, it is impossible to eliminate heavy metal contamination from cleaning chemicals, wafer handling jigs, tweezers, etc., or micro defects caused by thermal processes such as diffusion, oxidation, and annealing. Close to.

Heavy metal contamination, micro defects, etc. cause crystal defects during the heat treatment stage of the manufacturing process. This defect significantly degrades the performance of the manufactured semiconductor device or renders it inoperable. For example, increased leakage current in the p-n junction, reduced charge mobility in the active region, which reduces the speed in switching operations, etc. MOSFET (M
(O8 field effect transistor), this causes a variation in the threshold voltage. These effects on device performance are fatal for large-area devices. In this way, in order to manufacture large-area, highly integrated semiconductor devices, it is necessary to prevent heavy metal contamination and micro-defects that occur during the manufacturing process.
It is necessary to remove it from the area where it forms.

On the other hand, when crystal defects are externally introduced into a semiconductor such as a Si wafer at a very high density, when a heat treatment process is performed afterwards, heavy metals that were present in other regions are transferred to the areas where the crystal defects are present at a high density. Alternatively, it has been known for a long time that micro defects have the property of moving and becoming nests. Taking advantage of this property, high-density crystal defects are introduced externally into areas other than the regions where elements are formed within the St wafer, and heavy metals or minute defects that are contaminated and introduced into the wafer during the process are removed from the outside. A method has been considered in which the crystal defects present in the element region are removed by collecting the crystal defects at the introduced defect site, and this method is known as gettering technology.

Such a categorizing technique is basically a method of introducing high-d degree crystal defects into a region other than the element region from the outside by some method. Furthermore, the heat treatment step performed after introducing crystal defects plays an important role. Heat treatment at a high temperature is required to prevent the contaminating heavy metals from reaching the introduced high-density crystal defect areas. It is thought that during this high-temperature process, heavy metals move through the eight crystals to crystal defects and collect.

In this way, in order to produce a more effective grouping of heavy metals, the characteristics required of the categorizing technology are the introduction of high-density crystal defects, that is, the ability of heavy metals to move easily during high-temperature processing. The method of introducing the crystal strain of Narudame and the conflict with the subsequent heat treatment process, in other words, where in the LSI process should the process of introducing high-density crystal defects for scaling be inserted are two important points. Conceivable.

Based on the above, the following characteristics are considered to be required for the tsuttering technology.

(1) Avoid contaminating the wafer with odor during the process of introducing crystal defects for crystallization.

(2) This process can be performed at any stage of the LSI manufacturing process.

(3) It is possible to perform the operation multiple times if it is safe. Unfortunately, heavy metals are contaminated during the LSI manufacturing process.

A number of conventional methods have been reported as scaling techniques for removing micro defects and other crystal defects that may become seeds of crystal defects during future processes. The basis of this scaling technology is to introduce high-density crystal defects in regions other than the active region that forms the device within the wafer surface (especially the back surface is often used). Due to this high-density defect introduced from the outside, contaminant heavy metals, micro defects, etc. present in the active region move to this high-density defect site during the subsequent heat treatment process, and as a result, the active region forming the device becomes crystalline. The state is close to a perfect crystal with no defects.

As described above, the essence of the scaling technology is a high-density defect introduction technology of 6D, and it is necessary to be able to limit the introduction site to outside the region where the element is to be formed within the sea urchin. Conventionally, the following methods have been reported and studied as this more advanced gettering technology.

(1) A method in which strain is generated in the 81 crystal by diffusing impurity atoms such as phosphorus or boron at a high concentration, followed by heat treatment to generate aggressive crystal defects. For example, phosphorus or the like is diffused into the wafer surface using POCl2 as a source at a furnace temperature of 1100° C. or higher, and then further diffused at a furnace temperature of 1100° C. or higher to introduce high-density defects.

At this time, it is necessary to form a mask such as an oxide film that is thick enough to prevent phosphorus from penetrating through the region by diffusion.

(2) The method of lining the back of the wafer (111), pinging or scribing the wafer, the diameter is 0.5 μm to 2.0 μm.
There is a way to do this by spraying diamond particles of about 7 in diameter. These methods use some type of jig to create scratches on the back surface of the wafer, and introduce high-density crystal defects into the scratched areas.

In order to remove contaminant heavy metals, minute defects, etc. outside the area where the elements are formed within the wafer, it is necessary to remove contaminants from a limited area outside the element head area within the wafer in a clean condition that does not cause contamination. Moreover, it is necessary to introduce crystal defects whose throughput is less than AM.

The above (
The respective problems of the conventional techniques 1) and (2) are listed below.

(1) In the method (1) above, in order to diffuse impurity atoms to a high aIf, it is necessary to use a fairly thick conditioning film as a mask, but defects are already introduced during the formation of this oxide film. Ru. However, when performing heat treatment processes such as oxidation and annealing after high-concentration diffusion for crystals, it is necessary to prevent contamination of the active region by some method, taking into consideration the back-diffusion of impurities from this occupancy site. There is a need. In this way, in order to bring this ketering technology to fruition, it becomes necessary to use a diffusion mask and take countermeasures to prevent back-diffusion.

(2) The conventional method described in (2) above requires the use of jigs for wrapping and marking, and contamination from these jigs is unavoidable. Furthermore, it is difficult to introduce scaling operations in the middle of the manufacturing process. In order to effectively produce the scaling effect, it is important not only how to introduce high density defects for scaling, but also at what stage in the manufacturing process this operation is introduced.

In summary, in the conventional crystallization method to obtain the crystal Linda effect, a mask is applied during the subsequent heat treatment process in order to prevent contamination from crystal defects. It is necessary to keep it. Furthermore, since jigs and the like are used to prevent the introduction of density crystal defects, there is a problem in that it is necessary to prevent contamination from these jigs.

The present invention solves these problems of the conventional technology, keeps the wafer in a clean state, keeps the wafer in a clean state that does not have any influence on subsequent processes, and improves throughput (processing capacity per hour). ) An object of the present invention is to provide a method for manufacturing a semiconductor device having a process that can easily introduce high-density crystal defects.

The method for manufacturing a semiconductor device according to the present invention basically consists of (
1) a wafer cleaning process, (2) a process of introducing high-density crystal defects in areas other than the areas where elements are formed within the wafer, (3) a process of forming confections, and (4) a metal film for wiring. (
The present invention is characterized in that discharge plasma is utilized in the step (2) above, which includes the steps of forming and processing (p, t, etc.) and performing shifter 1 processing.

The actual 7i8i column will be explained in detail below.

First, we will explain the basics.

(1) Wafer cleaning process The wafer cleaning process consists of arithmetic cleaning and standard clean cleaning, including the removal of organic matter adhering to the wafer surface (the former) or the removal of harmful heavy metals before introducing the LSR7 manufacturing process. (1) to ensure the cleanliness of the wafer.

(2) Process of introducing heavy-density crystal defects to areas other than the element-forming region High-density crystal defects are introduced to wafer parts other than the element-forming region using discharge plasma.

In halogen-based or gas-based discharge plasma, in addition to high-energy electrons (eV), various atoms or molecular ions (having positive or negative charges),
Or there are a lot of excitons. By placing a wafer in such a plasma (for example, in the cannide region or anode region), atomic or molecular ions accelerated by the electric field that maintains this discharge collide with the wafer surface, creating a large number of defects. Introduced into the wafer. In addition, atoms (molecules) ions or i'J: Ih) J electrons and St
A rapid chemical reaction occurs within the wafer plane. Due to energy generation at this time, crystal defects are generated inside. Alternatively, there is stress due to internal strain introduced due to chemical reactions, etc. In this step, a large amount of i-crystal defects are introduced by utilizing the mechanism described above.

In this way, the halogen-based gas plasma can be used to
- The crystal defects introduced to the surface have the effect of attracting heavy metals or minute defects existing inside the Ueno when heat treatment is performed in the subsequent step (Step (3) described below). This is the scaling effect.

In the present invention, CXyY4-
Use y. However, X and Y are haloke elements (F, Ct
, Br, I, etc.), y is a number up to 4.

The patterns include CF + CF s B r.

This process is a clean process that does not contaminate the wafer.

(3) Process of forming a crystal The process of forming a crystal such as oxidation, ion implantation, annealing, etc. differs depending on whether the desired device is a bipolar crystal, an M, or an O8 element, but the basic The process is a combination of steps such as oxidation of the wafer, introduction of impurities, activation of diffusion, and formation of a thin film such as a polycrystalline silicon film by CVD. Between these processes, a cleaning process based on pure water cleaning and an etching process based on photolithography are inserted as needed.

(4) Processing process for forming metal films for wiring In the process for forming metal films for wiring, it is necessary to connect the semiconductor elements formed within the wafer surface in the processes to the north, and to connect the external power supply. Perform electrical wiring for introduction or transfer of input/output signals. As a result, sea urchin
・The elements formed on the inner chip are organically connected and can function as a single electronic device.

In the above, the step (2) of introducing high-density crystal defects for obtaining the scaling effect may be performed before the element forming step (3) or may be inserted during the step (3).

Next, a specific implementation sequence will be explained.

First Embodiment FIG. 1 shows the steps of an embodiment of the present invention for manufacturing a MOS diode.

After cleaning the S1 wafer 1, a protective silicon oxide film (81021
i) Form 2. Thereafter, high-density crystal defects are introduced into the back surface of the Si sea urchin 1 using a halocene gas waste paper plasma 3 (FIG. 1(a)).

Next, the protective S102 film 2 was coated with 10% of NH4/HF.
After removing the etch with a solution of /1, remove the dirt oxide film 4 with a solution of 7
Oxide is formed to a thickness of 00X (#!1 Figure (b)).

Thereafter, an AJ film 5 is deposited on the oxidized layer 4 for the gate and etched using photophosphorographic technology to form a MOS structure (FIG. 1(C)).

After depositing At as the ohmic electrode 6 on the back surface of the Si wafer 1, sintering is performed (at a temperature of 450° C. for 30 minutes) to form a MOS diode.

C-V of 1VfOs diode obtained in this way
Characteristics were measured. The interface state density (S+-8 film 02 interface) determined from this C-V llj edge is Q s s (c
m-2) is shown in Table 1. When forming a MOSFET using this dirt oxidation odor, the fluctuation in the threshold voltage of the MOSFET caused by the existence of this interface state is ΔV7
= qQss/Cox(V). Here, q is the unit charge of electrons, and Cox is the unit density due to the gate oxide film. As shown in this table, wafers subjected to dattering using this method have a ΔVT (0, 1), whereas wafers with dattering and wafers dattering by introducing puncture damage using glass beads have a ΔVT>0. .1.The threshold i of normal IVIO8FET is n
(Channel type) VT' = 0 for IVIO8FET
．． 5 to 0.8 (V), the threshold fluctuation caused by external causes during the manufacturing process, that is, ΔVT, is ΔVT
It is preferable that <0.1 (V). This embodiment fully satisfies this requirement.

Table 1 Measurement point: arbitrarily selected the center of the wafer 2. Third. 4th Embodiment Figures 2, 3 and 4 are +11], 08 respectively
The second aspect of the present invention for manufacturing FETs. 3rd and 4th
It is a diagram for explaining the steps of the implementation sequence.

In all of these examples, the back surface of the wafer was selected as the site for introducing high-density crystal defects, and the basic manufacturing process is the same. However, the difference is in the step of inserting the process of introducing high-density crystal defects to obtain the scaling effect.

Without further ado, the second implementation sequence shown in FIG. 2 will be explained.

Buffer S on the side of Si wafer 1 where elements are to be formed]
02 film 2 is applied, and crystal defects with a density for catering are introduced into the back surface thereof (FIG. 2(a)). A parallel plate plasma etching device with an electrode spacing of 6cnI8 degrees was used to generate discharge plasma. CFsBr is used as the discharge gas, and the gas pressure is 2 to 4 Pa.

The gas flow rate was 20 to 8 Q CC, the high frequency input for /'min N discharge was 500 W, and the processing time was 10 minutes. The wafer to be processed was set on the cathode side of the apparatus with the processing side, that is, the side to which the protective S + 021 layer 2 was not attached, facing up.

Next, a silicon nitride film (s13
N 4 film)]4 is selectively oxidized using a mask to form a silicon oxide iI>1 (s]o2rm) of 1 μm (FIG. 2(b)).

S+0 for the silicon nitride film 14 and the underlayer
After removing the 2i block, oxidation 1. li41μm
(Fig. 2(C)). Before and after this, ion implantation to control threshold blood (approximately IXio13 cm-2
).

Next, after applying P-doped polycrystalline silicon 17 for the case 1 and processing the case electrode, ion implantation for forming the source/drain portion 8 is performed (FIG. 2(d)).

Finally, after attaching an interlayer insulating film (S102, 5i5N4, etc.) 19, a contact hole is made in the silicon oxide film 151 and interlayer insulating film 9 above the source and layer capacitors 18.
Attach wiring metal such as 3i to complete MOSFET (
Figure 2(e)). If necessary, a back ohmic electric heater 21 is formed on the back side as shown in FIG. 2(e).

The embodiment shown in FIG. 3 is characterized in that the step of introducing high-density crystal defects, as shown in FIG. 3 (I/l), is inserted at a stage after the selective oxide film 15 is formed.

That is, the process of FIG. 3 (k/l is different from the embodiment of FIG. 2, but the other steps are the same as the corresponding steps of FIG. 2).

The implementation method shown in FIG. 4 is characterized in that the step of removing high-density crystal defects is inserted at the stage of the dirt oxide film fN (&. In other words, the step of FIG. 4 (C') is This embodiment is different from the embodiment shown in FIG. 2, and the other steps are the same as the corresponding steps shown in FIG.

In the embodiments shown in FIGS. 2 to 4, one gettering operation is performed in each case, but a method of introducing several gettering operations is also possible. For example, in the method shown in FIG. 4, the step shown in FIG. 3(b') can be inserted before the step (C') of performing the digitizing operation.

In the above example, the back side of the wafer was selected as the site for introducing the high-pitched v defect by digitizing, but it is also possible to select a site on the wafer surface other than the element formation area for this dragon.Implementation 1'' That is, 5th. 6th. The 7th funeral procession will be held in 5th place. 6th. It is shown in FIG.

These implementations 1+1J consist of almost the same steps except for the insertion point of the step of performing the scaling operation, that is, the step of introducing high-density crystal defects. In the process shown in FIG.
11'! , 32 are formed, and a color photoresist film 33 is formed.
is passed through the plasma step of the present method with the remaining on it (FIG. 5(a)). Next, 5i6 was formed by low pressure CVD method.
Selective oxidation is performed using the N4 film 34 as a mask (Fig. 5(b)
)). Then, the gate electrode 37 of IViO8 is formed of P-doped polycrystalline silicon, and ions are implanted for forming the source and drain (FIG. 5(C)). Finally, an interlayer insulation layer 39 (Si20) is formed, a contact hole is made, and one wiring is formed using a metal 40 such as At-3i (see Fig. 5).
d)). At this time, if necessary, h't is distilled on the back surface to form an ohmic junction 41.

FIG. 6 shows a stage where a selective one-wave oxidation film 35 has been formed leaving a high-density crystal defect introduction site, and a renost 36 is applied on top of the oxide film 35 and the plasma process of this method is not performed. (
This embodiment differs from the embodiment shown in FIG. 5 in b')).

The coating shown in FIG. 7 is a case of oxidation of the gate; at the stage of forming a layer and forming the gate electrode 37, renost is applied on the selective oxidation 35 and the gate electrode 437. It is different from the case 1+lJ shown in FIGS. 5 and 6 in that it undergoes a plasma process (FIG. 7 (b')).

By employing a catering process using discharge plasma, the present invention enables processing in a much cleaner state compared to conventional catering processes.

This has the advantage that this process can be introduced between any steps in the semiconductor device iLt manufacturing process.

In addition, by using a mask that can withstand discharge plasma, it is possible to carry out the patterning process at any location on the wafer surface. However, in the present invention, it is possible to pattern the same surface on which the element is formed, and there is diversity in the patterning process.

Furthermore, since the process uses discharge plasma, a large number of wafers can be set in the discharge area circle, making it possible to process multiple wafers at once. Therefore, according to the method of the present invention,
Very good throughput can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining in detail the present invention for manufacturing an M,OS diode, (a), (b),
(c)...The temple shows the cross section of the wafer in the main process. FIGS. 2 to 4 are detailed illustrations of the present invention for manufacturing MO8F'ET, and in these three cases, the region where high-density crystal defects are introduced is on the back side of the wafer. 5 to 7 are detailed illustrations of the present invention for manufacturing M-O8FETs, and these three embodiments show that the region where high-density crystal defects are introduced is on the surface on the wafer where the device will be formed. is on the same plane as 1,'11,3]...wafer, 2,12...protective silicon oxide im (5to2)pA), 3...discharge plasma, 4...ket oxide film, 5...
・AtI conversion, 6,21,4.1...Ohmic electrode, 14,34...Silicon nitride 1ll (S
] 5N4 (exchange), 15.35...Silicon oxide film (Si20 film), 16...Ion implantation for source and drain formation, 1.7.37...Polycrystalline silicon, etc. electrode, 18.38... source, drain part, 19.39... interlayer insulating film, 20, 40...
...All-pole wiring such as At-8T, 33...mask such as resist. Figure 2 (0) 2 + hand) Cow~3 (b+ 4 Figure 3 (b') fff!f:5 (e) (e) Figure 5 (0) S+bt (1)'+ (c )(c'1 (dl (d) Figure 7(') (C') (dl

Claims (1)

[Scope of Claims] (1) A wafer cleaning step, a step of introducing high-density crystal defects for categorization into a region other than the region in which elements are to be formed within the wafer, and a step of forming elements; In a method for manufacturing a semiconductor device, which includes steps of forming, processing, and sintering a metal film for wiring, the step of introducing high-density crystal defects may include introducing high-density crystal defects into a selected region other than the region where the element is to be formed. 1. A method of manufacturing a semiconductor device, characterized in that the step is a step of generating high-density crystal defects by colliding discharge plasma of a location-based gas. '(2) The halogen-based gas is CXyY, where X and Y are halogen elements, and y is a number up to 4.
, y, the method for manufacturing a semiconductor device according to claim (1). (3) The method of manufacturing a semiconductor device according to claim 11, wherein the step of introducing the high-density crystal defects is inserted into the step of forming the element.