CN111524796A - A silicon carbide epitaxial wafer in the preparation of a silicon carbide power device and a processing method thereof - Google Patents

Abstract

The invention provides a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device and a processing method thereof. A dielectric layer is deposited on the front and back of the silicon carbide epitaxial wafer respectively; and the dielectric layer on the front surface of the silicon carbide epitaxial wafer is etched, Then, the dielectric layer on the backside of the silicon carbide epitaxial wafer is removed; and ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer. The invention greatly reduces the warpage of the silicon carbide epitaxial wafer, reduces the wafer rejection rate, improves the photolithography process precision and the ion implantation processing precision, reduces the ion implantation wafer rejection rate and the fragmentation rate, and greatly improves the carbonization rate. Accuracy and pass rate of silicon epitaxial wafers; separate dielectric layers are formed on the front and back of the silicon carbide epitaxial wafer step by step, which offsets the material stress caused by the direct deposition of the dielectric layer on the front surface of the silicon carbide epitaxial wafer, which is the cause of the warping of the silicon carbide epitaxial wafer. The improvement of the curvature provides the basis; the cost is low, the efficiency is high, and it is suitable for silicon carbide epitaxial wafers of various specifications.

Description

A silicon carbide epitaxial wafer in the preparation of a silicon carbide power device and a processing method thereof

technical field

The invention relates to the technical field of power semiconductor devices, in particular to a silicon carbide epitaxial wafer in the preparation of silicon carbide power devices and a processing method thereof.

Background technique

The electrical parameters of the third-generation semiconductor silicon carbide (SiC) materials and traditional silicon (Si)-based semiconductor substrate materials are very different. SiC material has large thermal conductivity, wide band gap, high electron saturation velocity and breakdown voltage, low dielectric constant, these characteristics determine its high temperature, high frequency, high power semiconductor devices. Due to the application potential in such aspects, the current research and development focus in the semiconductor field has gradually shifted to silicon carbide materials. The physical parameters of silicon carbide material and silicon material are quite different. Because the diffusion coefficient of SiC material itself is very low, the traditional ion diffusion process makes the concentration of silicon carbide material do not change greatly after high temperature doping. In the actual process , the SiC material cannot be selectively doped by thermal diffusion. Even if the ion implantation process is used, the SiC material needs to be implanted at a high temperature, which is beneficial to obtain a higher ionization rate and can also repair the lattice damage. Therefore, high temperature ion implantation has become the preferred method for selective doping on SiC.

In the preparation of SiC devices, the SiC element doping or ion implantation process is: deposit a layer of SiO ₂ film on the surface of the SiC epitaxial wafer by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) method, and then use photolithography to form For the mesa pattern, the pattern is transferred to the SiO ₂ mask by etching. After removing the photoresist, high temperature ion implantation is performed on the SiC epitaxial wafer with the SiO ₂ pattern as the mask. The preparation of silicon carbide power devices by the above process requires the use of a thicker epitaxial layer of silicon carbide epitaxial wafers and a thicker dielectric film as a masking layer. However, the thick mask has a large stress, which is easy to cause the warpage of the epitaxial wafer and affect the light In addition, the high-temperature and high-energy ion implantation process easily introduces stress, which in turn causes the warpage of the epitaxial wafer during the ion implantation process, resulting in reduced machining accuracy and the risk of debris.

In the prior art, the prepared silicon carbide epitaxial wafer is usually put into the reaction chamber, kept at 650-1050 ° C for 10-30 minutes, and then cooled to ≤300 ° C for 10-15 minutes, and the silicon epitaxial wafer is taken out of the reaction chamber. The high-temperature annealing method reduces the warpage of the silicon carbide epitaxial wafer, but the warpage of the silicon carbide epitaxial wafer is still very large and the rejection rate is high.

SUMMARY OF THE INVENTION

In order to overcome the deficiencies of high warpage and high rejection rate of silicon carbide epitaxial wafers in the prior art, the present invention provides a processing method for silicon carbide epitaxial wafers in the preparation of silicon carbide power devices, including:

respectively depositing dielectric layers on the front side and the back side of the silicon carbide epitaxial wafer;

The dielectric layer on the front side of the silicon carbide epitaxial wafer is etched, and then the dielectric layer on the back side of the silicon carbide epitaxial wafer is removed;

Ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer.

The deposition of dielectric layers on the front and back of the silicon carbide epitaxial wafer, respectively, includes:

depositing a first dielectric layer on the front side of the silicon carbide epitaxial wafer;

depositing a second dielectric layer on the backside of the silicon carbide epitaxial wafer after a preset time after the formation of the first dielectric layer;

A third dielectric layer is deposited on the front surface of the silicon carbide epitaxial wafer after a predetermined time after the formation of the first dielectric layer.

The method of etching the dielectric layer on the front side of the silicon carbide epitaxial wafer, and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer, includes:

Coating photoresist on the third dielectric layer on the front side of the silicon carbide epitaxial wafer, and patterning the photoresist;

Etching the front surface of the silicon carbide epitaxial wafer by using the patterned photoresist as a mask, and removing the photoresist;

Coating photoresist on the front side of the silicon carbide epitaxial wafer;

Wet etching is performed on the second dielectric layer on the backside of the silicon carbide epitaxial wafer.

After the removal of the dielectric layer on the backside, the method further includes:

Remove the photoresist from the front side of the SiC epitaxial wafer.

The ion implantation on the front side of the etched silicon carbide epitaxial wafer includes:

Determine ion implantation dose and ion implantation temperature;

Ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer based on the dose and temperature.

After the ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer, the method further includes:

The third dielectric layer and the first dielectric layer are removed.

The deposition adopts plasma enhanced chemical vapor deposition method or low pressure chemical vapor deposition method.

The first dielectric layer, the second dielectric layer and the third dielectric layer are all one or a combination of at least two of silicon dioxide, silicon nitride, and polysilicon.

The thickness of the first dielectric layer is 0.2 μm˜10 μm;

The thickness of the second dielectric layer is 0.2 μm˜10 μm;

The thickness of the third dielectric layer is 0.2 μm˜6 μm.

The ion implantation dose is 1E11cm ^-2 to 1E18cm ^-2 ;

The ion implantation temperature is 25°C˜600°C.

Before depositing the dielectric layers on the front and back surfaces of the silicon carbide epitaxial wafer, respectively, it includes:

The silicon carbide epitaxial wafer is cleaned by using the RCA standard cleaning method to remove metals, organic substances and contaminants on the surface of the silicon carbide epitaxial wafer.

The invention also provides a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device, comprising: a front surface of the silicon carbide epitaxial wafer and a back surface of the silicon carbide epitaxial wafer;

The front surface of the silicon carbide epitaxial wafer and the back surface of the silicon carbide epitaxial wafer are respectively obtained according to the processing method.

Compared with the closest prior art, the technical solution provided by the present invention has the following beneficial effects:

In the method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices provided by the present invention, dielectric layers are respectively deposited on the front and back of the silicon carbide epitaxial wafer; the dielectric layer on the front surface of the silicon carbide epitaxial wafer is etched, and then removed. The dielectric layer on the back of the silicon carbide epitaxial wafer; the ion implantation on the front side of the etched silicon carbide epitaxial wafer greatly reduces the warpage of the silicon carbide epitaxial wafer and reduces the rejection rate;

The processing method provided by the invention improves the photolithography process precision and the ion implantation process precision, reduces the rejection rate and the fragmentation rate of the ion implantation, and greatly improves the precision and the qualified rate of the silicon carbide epitaxial wafer;

The processing method provided by the present invention forms respective dielectric layers on the front and back of the silicon carbide epitaxial wafer step by step, that is, firstly depositing a first dielectric layer on the front side of the silicon carbide epitaxial wafer, and then depositing a second dielectric layer on the back side of the silicon carbide epitaxial wafer Finally, a third dielectric layer is deposited on the front side of the silicon carbide epitaxial wafer, which offsets the material stress caused by the direct deposition of the dielectric layer on the front side, and provides a basis for improving the warpage of the silicon carbide epitaxial wafer;

After etching the third dielectric layer and the first dielectric layer according to the technical solution provided by the present invention, the stress on the front side of the silicon carbide epitaxial wafer is released, and the second dielectric layer on the back side becomes the main factor causing the warpage of the silicon carbide epitaxial wafer. The front side of the silicon carbide epitaxial wafer is coated with photoresist to protect the front side of the silicon carbide epitaxial wafer to prevent the front side of the silicon carbide epitaxial wafer from being corroded, and the second dielectric layer on the back of the silicon carbide epitaxial wafer is wet-etched, which effectively reduces the amount of silicon carbide. The warpage of the epitaxial wafer;

The invention provides low cost and high efficiency, and is suitable for silicon carbide epitaxial wafers of various specifications.

Description of drawings

1 is a flowchart of a processing method for a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device according to an embodiment of the present invention;

2 is a schematic diagram of depositing a first dielectric layer on the front side of a silicon carbide epitaxial wafer in an embodiment of the present invention;

3 is a schematic diagram of depositing a second dielectric layer on the backside of a silicon carbide epitaxial wafer in an embodiment of the present invention;

4 is a schematic diagram of depositing a third dielectric layer on the front side of a silicon carbide epitaxial wafer in an embodiment of the present invention;

5 is a schematic diagram of coating photoresist on the front side of the third dielectric layer in an embodiment of the present invention;

6 is a schematic diagram of patterning processing of photoresist in an embodiment of the present invention;

7 is a schematic diagram of etching the front surface of a silicon carbide epitaxial wafer by using the patterned photoresist as a mask in an embodiment of the present invention;

8 is a schematic diagram of removing the photoresist after etching the front surface of the silicon carbide epitaxial wafer in an embodiment of the present invention;

9 is a schematic diagram of coating photoresist on the front side of a silicon carbide epitaxial wafer in an embodiment of the present invention;

10 is a schematic diagram of wet etching the second dielectric layer in an embodiment of the present invention;

11 is a schematic diagram of removing the photoresist after wet etching the second dielectric layer in the embodiment of the present invention;

12 is a schematic diagram of ion implantation on the front side of the etched silicon carbide epitaxial wafer according to an embodiment of the present invention;

13 is a schematic diagram of a silicon carbide epitaxial wafer obtained after removing the third dielectric layer and the first dielectric layer in an embodiment of the present invention;

In the figure, 1. Silicon carbide epitaxial wafer, 2. The first dielectric layer, 3. The sample obtained after coating the first dielectric layer, 4. The second dielectric layer, 5. The sample obtained after coating the second dielectric layer, 6. The third dielectric layer, 7. The sample obtained by coating the third dielectric layer, 8. The photoresist coated on the sample 7, 9. The sample obtained after patterning the photoresist 8, 10. The sample obtained by etching the front side of the silicon carbide epitaxial wafer with the photoresist after photoresist as a mask, 11. The sample obtained by removing the photoresist 8, 12. Coating on the front side of the silicon carbide epitaxial wafer before removing the dielectric layer on the back side 13. The sample after coating the photoresist 12, 14. The sample obtained by wet etching the second dielectric layer, 15. The sample obtained by removing the photoresist 12, 16. After the etching The sample obtained by ion implantation on the front side of the silicon carbide epitaxial wafer.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings.

The embodiment of the present invention provides a method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices. The specific flowchart is shown in FIG. 1 , and the specific process is as follows:

S101: depositing a dielectric layer on the front and back of the silicon carbide epitaxial wafer 1 respectively;

S102: etching the dielectric layer on the front side of the silicon carbide epitaxial wafer 1, and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer 1;

S103 : performing ion implantation on the front surface of the etched silicon carbide epitaxial wafer 1 .

Before the dielectric layers are deposited on the front and the back of the silicon carbide epitaxial wafer 1 respectively, the silicon carbide epitaxial wafer 1 needs to be cleaned by the RCA standard cleaning method to remove metals, organics and contaminants on the surface of the silicon carbide epitaxial wafer 1 . The specific cleaning process is as follows:

Soak the silicon carbide epitaxial wafer 1 in SC1 cleaning solution, first prepare a hydrofluoric acid solution (HF:H ₂ O=1:10), then clean and dry the sample holder, and place the sample 3 on the holder.

3# solution (sulfuric acid: H ₂ O ₂ =3:1) was prepared. It should be noted that the sulfuric acid is added last, and another container is used to boil the water at the same time. After the 3# solution is completed, put the sample 3 into the 3# solution, boil and wash it for about 15 minutes, and take it out; heat the sample 3 to 250 ℃, pick up the support with the sample 3 and cool it for a while, and then put the support into hot water to flush.

Prepare 1# solution (ammonia: H ₂ O ₂ : H ₂ O=1:1:5-1:1:7): Pour the first two into hot water, heat to 75-85°C, and the time is about 10 ~20min; then put the bracket with sample 3 into 1# solution for about 15min, then take out the bracket and put it in hot water for flushing.

Prepare 2# solution (HCl: H ₂ O ₂ : H ₂ O=1:1:5): pour the first two into hot water. After the preparation is completed, the holder with sample 3 is taken out and placed in solution 2# for about 15 minutes. The stand is then removed, placed in hot water and flushed.

Sample 3 was rinsed with 10% hydrofluoric acid for about 5 to 30s to remove the oxide layer on the surface of sample 3. Then rinse with deionized water for about 20 minutes.

After the sample is cleaned by the RCA cleaning method, a dielectric layer is deposited on the front and back of the silicon carbide epitaxial wafer 1 respectively, which specifically includes:

A first dielectric layer 2 is deposited on the front side of the silicon carbide epitaxial wafer 1, as shown in FIG. 2, to obtain the sample 3 in FIG. 2, the thickness of the first dielectric layer 2 is 0.2 μm to 10 μm; in the embodiment of the present invention, the front side deposition The first dielectric layer 2 is a 1.5 μm SiO ₂ film; the first dielectric layer 2 deposited on the front side of the silicon carbide epitaxial wafer 1 can protect the front side of the silicon carbide epitaxial wafer 1 to prevent contamination and scratches. Multiple film formation can avoid the influence of the stress of the direct growth of the thick film, and effectively control the warpage of the silicon carbide epitaxial wafer 1 .

After a preset time after the first dielectric layer 2 is formed, a second dielectric layer 4 is deposited on the back of the silicon carbide epitaxial wafer 1, as shown in FIG. 3, to obtain the sample 5 in FIG. 3; after the first dielectric layer 2 on the front is formed , it is necessary to deposit the second dielectric layer 4 on the back of the silicon carbide epitaxial wafer 1 as soon as possible. In this embodiment, within 15 minutes after the first dielectric layer 2 is formed, the second dielectric layer 4 is deposited on the back of the silicon carbide epitaxial wafer 1. The thickness of the second dielectric layer 4 is 0.2 μm˜10 μm, and in the embodiment of the present invention, the second dielectric layer 4 is a 2.5 μm SiO ₂ film;

After a preset time after the formation of the first dielectric layer 2, a third dielectric layer 6 is deposited on the front side of the silicon carbide epitaxial wafer 1, as shown in FIG. 4, to obtain the sample 7 in FIG. 4, and the thickness of the third dielectric layer 6 is 0.2 μm˜6 μm, in this embodiment, the third dielectric layer 6 is a 1 μm SiO ₂ film.

The above-mentioned deposition medium layer can adopt plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, PECVD) or low pressure chemical vapor deposition method (Low Pressure Chemical Vapor Deposition, LPCVD), the embodiment of the present invention adopts PECVD method to deposit the first medium Layer 2 , second dielectric layer 4 and third dielectric layer 6 . The deposition of the third dielectric layer 6 meets the masking requirements of the high temperature and high energy ion implantation film.

The above S101 is divided into two layers of dielectric layers on the front side. It is also possible to deposit a thicker dielectric layer on the front side, and then deposit another layer of dielectric layers on the back side. When depositing a layer of dielectric layers on the front side and the back side , the thickness of the dielectric layer deposited on the front side may be 0.2 μm˜3 μm, and the thickness of the dielectric layer deposited on the back side may be 0.2 μm˜10 μm. Regardless of whether the front-side dielectric layer is deposited once or in two separate depositions, the backside-deposited dielectric layer is used to balance the warpage of the silicon carbide wafer caused by the front-side dielectric layer deposition.

The dielectric layer on the front side of the silicon carbide epitaxial wafer 1 is etched, and then the dielectric layer on the back side of the silicon carbide epitaxial wafer 1 is removed, including:

A photoresist 8 is coated on the third dielectric layer 6 on the front side of the silicon carbide epitaxial wafer 1, as shown in FIG. 5; after that, the photoresist 8 is patterned, as shown in FIG. 6, to obtain the sample 9 in FIG. 6 ; In the embodiment of the present invention, before the front side of the third dielectric layer 6 is coated with photoresist 8, a layer of HMDS (ie hexamethyldisilazane) tackifier is applied on the front side of the sample, and the model of the photoresist 8 is AZ703 , any other positive photoresist can also be used, and the photoresist 8 can be coated by an automatic gluing method or a manual gluing method. The patterning process includes vapor phase base film formation (HMDS), glue coating, pre-bake, exposure, post-bake, development, hardening and development inspection.

Using the patterned photoresist as a mask, the front side of the silicon carbide epitaxial wafer 1 is etched, as shown in FIG. 7, to obtain the sample 10 in FIG. 7, and the photoresist is removed, as shown in FIG. 8, Sample 11 is obtained; dry etching or wet etching is performed on the front surface of the silicon carbide epitaxial wafer 1 by using the patterned photoresist as a mask to obtain an ion implantation mask pattern, and at the same time, the stress of the front dielectric layer is reduced on the silicon carbide epitaxy. The effect of sheet warpage.

A photoresist 12 is coated on the front side of the silicon carbide epitaxial wafer 1, as shown in FIG. 9, to obtain a sample 13;

The second dielectric layer 4 on the backside of the silicon carbide epitaxial wafer 1 is wet-etched, as shown in FIG. 10 , to obtain a sample 14, and then the photoresist 12 is removed, as shown in FIG. In the embodiment of the present invention, a layer of HMDS (ie, hexamethyldisilazane) tackifier is coated on the front side of the sample 11 , and then a photoresist 12 is coated on the front side of the silicon carbide epitaxial wafer 1 . In the embodiment of the present invention, the BOE etching solution is used to perform wet etching on the second dielectric layer 4, that is, the BOE etching solution is used to remove the second dielectric layer 4 on the backside.

Ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer 1, including:

Determine ion implantation dose and ion implantation temperature;

Based on the dose and temperature, ion implantation is performed on the front side of the etched silicon ^{carbide epitaxial} wafer 1, as shown in FIG. 12, to obtain sample 16; , the type of implanted ions is not limited;

After ion implantation is performed on the front surface of the etched silicon carbide epitaxial wafer 1 , the third dielectric layer 6 and the first dielectric layer 2 are removed to obtain the processed silicon carbide epitaxial wafer 1 , as shown in FIG. 13 .

The first dielectric layer 2 , the second dielectric layer 4 and the third dielectric layer 6 are all one or a combination of at least two of silicon dioxide, silicon nitride, and polysilicon.

The practical silicon carbide epitaxial wafer in the embodiment of the present invention has a diameter of 100 mm, 150 mm, 200 mm or more, and a thickness of 0-200 μm. The silicon carbide epitaxial wafer 1 is processed by using the processing method for the silicon carbide epitaxial wafer 1 in the preparation of the silicon carbide power device provided by the embodiment of the present invention, and the front side of the silicon carbide epitaxial wafer and the back side of the silicon carbide epitaxial wafer are obtained; Sheet warpage is greatly reduced, and sheet rejection is low.

For the convenience of description, each part of the above device is divided into various modules or units by function and described respectively. Of course, when implementing the present application, the functions of each module or unit may be implemented in one or more software or hardware.

As will be appreciated by those skilled in the art, the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block in the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions The apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowcharts and/or the block or blocks of the block diagrams.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Those of ordinary skill in the art can still modify or equivalently replace the specific embodiments of the present invention with reference to the above embodiments. Any modifications or equivalent replacements that depart from the spirit and scope of the present invention fall within the protection scope of the present invention for which the application is pending.

Claims (12)

1. a processing method of silicon carbide epitaxial wafer in the preparation of silicon carbide power device, is characterized in that, comprises: respectively depositing dielectric layers on the front side and the back side of the silicon carbide epitaxial wafer; The dielectric layer on the front side of the silicon carbide epitaxial wafer is etched, and then the dielectric layer on the back side of the silicon carbide epitaxial wafer is removed; Ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer. 2. The method for processing a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device according to claim 1, wherein the deposition of a dielectric layer on the front side and the back side of the silicon carbide epitaxial wafer, respectively, comprises: depositing a first dielectric layer on the front side of the silicon carbide epitaxial wafer; depositing a second dielectric layer on the backside of the silicon carbide epitaxial wafer after a preset time after the formation of the first dielectric layer; A third dielectric layer is deposited on the front surface of the silicon carbide epitaxial wafer after a predetermined time after the formation of the first dielectric layer. 3. The processing method of silicon carbide epitaxial wafer in the preparation of silicon carbide power device according to claim 2, characterized in that, the dielectric layer on the front side of the silicon carbide epitaxial wafer is etched, and then the back surface of the silicon carbide epitaxial wafer is removed. Dielectric layers, including: Coating photoresist on the third dielectric layer on the front side of the silicon carbide epitaxial wafer, and patterning the photoresist; Etching the front surface of the silicon carbide epitaxial wafer by using the patterned photoresist as a mask, and removing the photoresist; Coating photoresist on the front side of the silicon carbide epitaxial wafer; Wet etching is performed on the second dielectric layer on the backside of the silicon carbide epitaxial wafer. 4. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 3, wherein after removing the dielectric layer on the backside, the method further comprises: Remove the photoresist from the front side of the SiC epitaxial wafer. 5. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 3, wherein the ion implantation on the front side of the etched silicon carbide epitaxial wafers comprises: Determine ion implantation dose and ion implantation temperature; Ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer based on the dose and temperature. 6. The method for processing a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device according to claim 5, wherein after the ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer, the method further comprises: The third dielectric layer and the first dielectric layer are removed. 7 . The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 2 , wherein the deposition adopts a plasma enhanced chemical vapor deposition method or a low pressure chemical vapor deposition method. 8 . 8. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 2, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are silicon dioxide, nitrogen One or a combination of at least two of silicon carbide and polysilicon. 9 . The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 2 , wherein the thickness of the first dielectric layer is 0.2 μm˜10 μm; 10 . The thickness of the second dielectric layer is 0.2 μm˜10 μm; The thickness of the third dielectric layer is 0.2 μm˜6 μm. 10 . The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 5 , wherein the ion implantation dose is 1E11 cm ⁻² to 1E18 cm ⁻² ; 11 . The ion implantation temperature is 25°C˜600°C. 11 . The method for processing a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device according to claim 1 , wherein, before respectively depositing a dielectric layer on the front side and the back side of the silicon carbide epitaxial wafer, the method comprises: The silicon carbide epitaxial wafer is cleaned by using the RCA standard cleaning method to remove metals, organic substances and contaminants on the surface of the silicon carbide epitaxial wafer. 12. A silicon carbide epitaxial wafer in the preparation of a silicon carbide power device, characterized in that it comprises: a front surface of the silicon carbide epitaxial wafer and a back surface of the silicon carbide epitaxial wafer; The front surface of the silicon carbide epitaxial wafer and the back surface of the silicon carbide epitaxial wafer are respectively obtained according to the processing method according to any one of claims 1-9.

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