JPH10261593A - Manufacture of semiconductor device, semiconductor-manufacturing device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the mechanical strength of a semiconductor substrate from decreasing due to ion implantation and a succeeding heat treatment by setting at least the conditions of ion implantation so that a critical stress where the semiconductor substrate is elastically deformed becomes larger than the maximum stress in the semiconductor substrate. SOLUTION: At least the conditions of an ion implantation process are set so that a stress where a semiconductor substrate is elastically deformed becomes larger than the maximum stress in the substrate. For example, by implanting ions while, for example, the surface temperature of an Si substrate 1 is retained at a low temperature that is equal to or less than a specific temperature and maintaining a low temperature, the move of a point defect cannot occur easily even if one portion of the kinetic energy of ions is replaced by a thermal energy. A primary defect 2 after implanting ions becomes only a point defect and can be recovered by a succeeding heat treatment. Also, by increasing a temperature-increasing speed, the generation of a secondary defect 3 can be effectively suppressed. By maintaining the substrate temperature when implanting ions at a low temperature, the reduction in the substrate temperature can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, a semiconductor manufacturing apparatus, and a semiconductor device characterized by an ion implantation and a subsequent heat treatment step.

[0002]

2. Description of the Related Art In recent years, a large-scale integrated circuit (LSI) formed by integrating a large number of transistors, resistors, and the like as an electric circuit and integrating them on a single chip has been frequently used in important parts of computers and communication devices. . For this reason, the performance of the entire device is greatly related to the performance of the LSI alone. The performance of the LSI alone can be improved by increasing the degree of integration, that is, by miniaturizing the elements.

The element can be miniaturized by optimizing the ion implantation and the subsequent heat treatment (annealing) when forming a diffusion layer such as a source / drain diffusion layer. Thereby, for example, a MOS transistor having a shallow source / drain diffusion layer of 0.2 μm or less can be realized.

In order to form a shallow diffusion layer, it is necessary to not only distribute impurity atoms shallowly during ion implantation, but also to form a shallow diffusion layer.
It is necessary to set a small heat budget so that impurities do not diffuse deeply in the subsequent heat treatment. However, when the thermal budget is reduced, crystal defects are not sufficiently recovered and remain.

On the other hand, when a failure analysis of an LSI is performed, a defective LSI may have a large Pn junction leak current in a part of the cell, and may have extremely poor charge retention characteristics. When the pn junction leakage current is large, crystal defects such as dislocations are often present.

This kind of crystal defect is often found near a region where various materials are embedded in a semiconductor substrate such as a trench capacitor and a trench element isolation. The reason for this is that when a heterogeneous substance is embedded in a semiconductor substrate, the thermal expansion coefficient of the heterogeneous substance (embedded substance) differs from that of the substrate semiconductor. This is because thermal stress occurs at the center.

[0007]

The strength of the semiconductor substrate is as follows.
It gradually decreases every time through the LSI process. The present inventor, in order to investigate the cause, every time through the LSI process,
It was examined how the mechanical strength of the Si substrate (Si strength substrate) and the maximum stress inside the Si substrate (the maximum stress inside the Si substrate) change.

FIG. 7 shows the result. FIG. 7 is a graph showing the S / S in each process when an LSI is created by a conventional manufacturing method.
It shows the i-substrate strength and the maximum stress in the Si substrate. In the figure,
The horizontal axis represents typical LSI processes, and the dotted line represents the strength of the Si substrate immediately after each process, and the straight line represents the maximum stress in the Si substrate.

FIG. 7 shows that the maximum stress in a Si substrate is
Through the film forming process of Si ₃ N ₄ film and SiO ₂ film by
It can be seen that the number increases after a heat treatment step after ion implantation. Here, although the maximum stress in the Si substrate is repeatedly increased and decreased with the progress of the process, it is not monotonically increased.

On the other hand, the strength of the Si substrate generally decreases monotonically with each step. Defects that greatly affect the slip and pn junction characteristics occur at the step indicated by the arrow in FIG. 7, where it can be seen that the maximum stress in the Si substrate exceeds the Si substrate strength. That is, when the maximum stress in the Si substrate, which fluctuates with respect to the strength of the one Si substrate at the price, exceeds, the Si substrate undergoes plastic deformation, and a large defect occurs.

FIG. 7 shows that a large decrease in the strength of the Si substrate is caused by ion implantation. The recovery from implantation damage occurs by the subsequent heat treatment, and the Si substrate strength is slightly increased. However, in the case of the second ion implantation,
The increase in the strength of the Si substrate due to the subsequent heat treatment is very small. The reason why the strength of the Si substrate decreases is considered as follows.

When ion implantation is performed, point defects (Frenkel defect type defects) are formed in the Si substrate. Although the point defect is basically recovered by the subsequent heat treatment, a part of the point defect is combined to become a dislocation.

However, in fact, during the ion implantation process, point defects are united to generate a defect (defect cluster) larger than the point defect. Since the defect cluster is more stable in terms of energy than the point defect, it is difficult to recover by the heat treatment after the ion implantation and tends to remain as larger dislocation. The generation of such large dislocations lowers the strength of the Si substrate. This is shown in FIG.

FIG. 8 (a) shows an uncooled or water-cooled Si
As ions 33 are applied to the substrate 31 at about 20 to 40 keV.
This shows a state in which about 5 × 10 ¹⁵ cm ^{−2 is} implanted. The beam current is about 10 to 20 mA. At this time, the temperature of the surface of the Si substrate 31 during the ion implantation is 25 to 6
It is about 0 ° C.

The first defects caused by the ion implantation are point defects such as vacancies and interstitial atoms generated at the moment when As ions are implanted into the Si substrate. Further, since a part of the kinetic energy of the ions replaces the thermal energy, the point defect can be given thermal energy.

As a result, the vacancies and interstitial atoms can move slightly. As a result, near the bottom of the ion-implanted layer in a quasi-amorphous state, some recovery of point defects occurs due to recombination of vacancies and interstitial atoms. Defect clusters are also generated due to the bonding between inter-atoms.

Further, the implanted ions located at the foot (substrate side) of the ion implantation distribution are liable to diffuse between lattices at the back of the substrate even during the ion implantation, thereby forming defect clusters. . In this way, a primary defect 32 composed of a defect cluster which is larger than the point defect and is more stable in terms of energy is formed.

FIG. 8B shows a state where the Si substrate 31 after the above-described ion implantation is subjected to a heat treatment in a nitrogen atmosphere at 850 ° C. for 30 minutes. From the figure, it can be seen that the primary defect 32 is almost recovered, but instead a secondary defect 34 such as a dislocation loop, which is a defect larger than the primary defect 32, is formed.

FIG. 8C shows a state in which the second As ion implantation is performed. From the figure, it can be seen that the primary defect 32 is formed as in the case of the first As ion implantation.

FIG. 8D shows a second heat treatment in a nitrogen atmosphere at 850 ° C. for 30 minutes. From the figure, it can be seen that the primary defect 32 has recovered, but the secondary defect 34 has grown into a larger secondary defect 34 '.

Examining the interlayer relation with the strength of the Si substrate,
The strength of the i-substrate decreases once when the primary defect 32 is formed by the first ion implantation, but the strength of the Si substrate increases by an amount corresponding to the disappearance of the primary defect 32 in the subsequent heat treatment.

Then, the primary defects 32 are formed again by the second ion implantation, and the strength of the Si substrate is greatly reduced. The primary defect 32 is recovered by the subsequent heat treatment, but unlike the case of the first ion implantation, since the secondary defect 34 exists, it becomes a nucleus to form a larger secondary defect 34 '. In addition, the strength of the Si substrate hardly increases.

In this state, when a stress of a certain magnitude or more is applied, the displacement of the substrate strength is hindered by the secondary defects 34 '(large dislocations), so that plastic deformation easily occurs, and even larger crystal defects are generated. It grows, leading to an increase in pn junction leakage current and the like.

That is, when the ion implantation and the heat treatment are repeated, the strength of the Si substrate decreases, and the stress that causes the plastic deformation of the Si substrate eventually becomes smaller than the maximum stress in the Si substrate, causing a large crystal defect. This causes problems such as an increase in pn junction leakage current.

As described above, in the conventional method, even if heat treatment is performed after ion implantation into the Si substrate, crystal defects in the Si substrate cannot be effectively reduced. There was a problem that the strength was greatly reduced.

Japanese Patent Application Laid-Open No. 03-66122 discloses a method for lowering the temperature of a wafer stage during ion implantation. Further, Japanese Patent Application Laid-Open No. 04-162618 discloses a method of rapidly heating after ion implantation at a low wafer stage temperature. However, these conventional methods cannot completely reduce crystal defects. Further, there has been a problem that H ₂ O remaining in the ion implanter adversely affects the surface of the semiconductor substrate.

The present invention has been made in consideration of the above circumstances, and has as its object to provide a method of manufacturing a semiconductor device capable of preventing a decrease in mechanical strength of a semiconductor substrate due to ion implantation and subsequent heat treatment. It is possible to provide a semiconductor manufacturing apparatus that is effective for implementing the method.

[0028]

[Means for Solving the Problems]

[Configuration] In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes an ion implantation step of implanting ions into a semiconductor substrate, and a heat treatment step of performing a heat treatment on the semiconductor substrate. Or, during the ion implantation step and after the heat treatment step, at least the conditions of the ion implantation step are set such that a critical stress at which plastic deformation occurs in the semiconductor substrate is larger than a maximum stress in the semiconductor substrate. It is characterized by the following.

Further, the semiconductor manufacturing apparatus of the present invention has an ion implantation means for implanting ions into a semiconductor substrate accommodated in a container, and a temperature of the surface of the semiconductor substrate when implanting ions into the semiconductor substrate. The semiconductor device is characterized by comprising: a substrate temperature control means for maintaining a low temperature equal to or lower than a predetermined temperature; and a heat treatment means for performing a heat treatment on the semiconductor substrate into which the ions have been implanted.

Further, the semiconductor device of the present invention is characterized in that the semiconductor substrate having the diffusion layers of different conductivity types or the diffusion layers of different depths has a maximum strength of 500 MPa or more.

[Operation] As described above, the present inventor examined the cause of the strength of the semiconductor substrate gradually decreasing every time the LSI process was performed.
It was investigated how the Si substrate strength and the maximum stress in the Si substrate change.

As a result, it was found that by repeating the ion implantation and the heat treatment, a large defect was formed in the Si substrate, and the strength of the Si substrate was reduced. And such S
When the critical stress at which a plastic change occurs in the Si substrate due to a decrease in i-substrate strength is smaller than the maximum stress in the Si substrate,
Large crystal defects occur, which causes problems such as an increase in pn junction leakage current.

Therefore, the present invention adopts a configuration in which at least the conditions of the ion implantation step are set such that a stress at which a plastic change occurs in the semiconductor substrate is larger than a maximum stress in the semiconductor substrate. .

Specifically, for example, ions are implanted into the semiconductor substrate while the surface temperature of the semiconductor substrate is maintained at a low temperature equal to or lower than a predetermined temperature. Further, a heat trap is installed in the end station where the semiconductor substrate is installed.
This heat trap forms a lower temperature state than the surface of the semiconductor substrate in order to prevent frost caused by residual H ₂ O from adhering to the surface of the semiconductor substrate.

By maintaining the temperature at a low temperature, even if a part of the kinetic energy of the ions is replaced by thermal energy, the movement of point defects hardly occurs. The generation of defect clusters due to recombination is completely or sufficiently suppressed. In addition, because the heat trap is in the end station,
Frost can be prevented from adhering to the surface of the semiconductor substrate.

As a result, the primary defects after ion implantation are almost only point defects. Such a primary defect can be completely or almost completely recovered by a subsequent heat treatment. Therefore, it is possible to prevent the occurrence of a large defect that causes a decrease in substrate strength.

Further, in addition to the above conditions, it is preferable to increase the temperature rising rate in the heat treatment. By increasing the heating rate, the temperature range in which secondary defects are likely to be formed can be quickly passed, so that the occurrence of secondary defects can be more effectively suppressed. In this regard, a further effect can be obtained by installing a heat trap in the end station.

Further, the semiconductor manufacturing apparatus according to the present invention includes:
The surface of the semiconductor substrate at the time of ion implantation can be kept at a low temperature so that frost does not adhere to the surface. Therefore, the method for manufacturing a semiconductor device according to the present invention can be easily implemented, and a semiconductor device can be obtained.

[0039]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) The inventor of the present invention installed a (100) Si substrate in an end station provided with a heat trap to prevent frost from adhering to the substrate surface, and applied As ions of about 20 to 40 keV to 3 ×. About 10 ¹⁵ cm ^{-2 was} injected. The substrate temperature at the time of ion implantation was set at eight points within the range of -180 to 200 ° C. And RBS (Rutherford Back
He ion was implanted by Spectroscopy) to perform channeling measurement.

FIG. 1 shows the measurement results. From FIG.
It can be seen that immediately after ion implantation, the lower the substrate temperature, the higher the defect density and the worse the crystallinity. However, when the heat treatment is performed at 900 ° C. for 30 minutes, the lower the substrate temperature, the lower the defect density.

In particular, when the substrate temperature is as low as 20 ° C. or less even during the ion implantation, the defect density is sufficiently low.
When the substrate temperature is as low as −100 ° C. or less, the defect density is 0% in the range of the measurement accuracy.

The result is that atoms are harder to move as the substrate temperature is lower. Therefore, even if a part of the kinetic energy of the ions is replaced by thermal energy, the point defects present separately after the ion implantation move, Coalescence is suppressed,
This means that generation of defect clusters is suppressed.

These discrete point defects (primary defects)
Is more unstable in terms of energy than the defect cluster, and is completely recovered by the heat treatment after the ion implantation, and the implantation damage is repaired. That is, the Si that has become amorphous due to the ion implantation substantially returns to the original single crystal Si.

As described above, according to the present embodiment, the generation of defect clusters can be sufficiently suppressed by maintaining the substrate temperature at the time of ion implantation at a low temperature, so that a decrease in substrate strength can be effectively prevented. . Such a Si substrate without a decrease in substrate strength is less likely to warp and is effective for fine processing.

In this embodiment, the case of the Si substrate has been described. However, the defect density of other semiconductor substrates is sufficiently low at a substrate temperature of 20 ° C. or less.
At a substrate temperature of 0 ° C. or lower, the defect density becomes 0% in the range of the measurement accuracy.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 11 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment. This embodiment is an example in which the ion implantation and the heat treatment of the first embodiment are repeated twice.

First, with the substrate surface temperature kept at a temperature lower than room temperature, preferably at a temperature of -60 ° C. or lower,
As shown in FIG. 2A, the acceleration energy is 20 to 40 ke.
As ions 3 are implanted into the Si substrate 1 under the conditions of about V and a dose of 3 to 5 × 10 ¹⁵ cm ⁻² . The primary defects 2 generated by the ion implantation are point defects such as vacancies and interstitial atoms generated at the moment when As ions are implanted into the Si substrate 1.

Here, the beam current is about 10 to 20 mA, but by using a heat sink susceptor having high thermal conductivity, a state in which the surface temperature of the Si substrate 1 is maintained at the above-mentioned temperature during ion implantation is realized. doing.

Next, as shown in FIG. 2B, heat treatment is performed at about 850 to 900 ° C. for 30 minutes in a nitrogen atmosphere.
When applied to 1, primary defect 2 is completely recovered. Next, FIG.
As shown in c), a second ion implantation is performed. At this time, as in the case of the first ion implantation, the surface temperature of the Si substrate 1 is maintained at a low temperature during the ion implantation.

Next, as shown in FIG. 2D, a second heat treatment (nitrogen atmosphere, 850 to 900 ° C., 30 minutes) is performed. As shown in FIG. 2D, in the secondary defects 3 generated by the second ion implantation and heat treatment, only small dislocations slightly remain.

FIG. 3 shows an LSI using the method of this embodiment.
Mechanical strength of Si substrate (Si
2 shows the maximum stress inside the Si substrate (the maximum stress in the Si substrate). The strength of the Si substrate is indicated by a dotted line, and the maximum stress in the Si substrate is indicated by a straight line. The strength of the Si substrate decreases once at the stage where a primary defect (point defect) has occurred in the first ion implantation, but the primary defect is almost completely recovered by a subsequent heat treatment.
The Si substrate strength has returned to the state before ion implantation.

When a point defect is introduced by the second ion implantation, the strength of the Si substrate is greatly reduced. However, the crystal is recovered to 90% or more of perfect crystal by the second heat treatment. The intensity has returned to a state close to that before the second ion implantation.

This means that unlike the conventional method, no large defects (secondary defects) were generated in the Si substrate even after the second heat treatment. A plurality of 0.2 μm-square n ⁺ / p junctions as shown in FIG. 4 were formed by two ion implantations and heat treatments of the present embodiment, and the average leakage current (nA / piece) per junction was examined. As a result, the value was as low as 10 (nA / piece) at the application of 5 V, which could be reduced by about 3 to 4 digits as compared with the conventional method.

In this embodiment, the case of performing the ion implantation and the heat treatment twice is described. However, even in the case of the ion implantation and the heat treatment performed three or more times, the Si substrate strength can be more effectively reduced than the conventional method. Can be suppressed.

Third Embodiment In general, when a shallow diffusion layer of 0.2 μm or less, for example, a source / drain diffusion layer is formed, if the heat treatment time is 30 minutes or more, 800 μm or less.
It is necessary to keep the temperature below ° C. However, even if the heat treatment temperature is lowered, if it is a short time within 1 minute, 900-
Heat treatment at about 950 ° C. (high-speed temperature increase heat treatment) is possible. This embodiment is an example in which such a high-speed heat treatment is combined with the low-temperature ion implantation of the first embodiment.

According to the present embodiment, the time during which the crystal defect (primary defect) easily grows into a secondary defect by the high-temperature heating treatment, that is, the temperature range of 600 to 700 ° C., is sufficient. As a result, the defect density can be reduced more effectively. Further, the deterioration speed of the semiconductor substrate (in the case of a decrease in substrate strength per process) can be reduced.

Further, by using such low-temperature ion implantation and high-speed heat treatment, impurities can be prevented from being diffused deeply, so that a shallow diffusion layer, for example, a source / drain diffusion of 0.2 μm or less can be easily formed. it can. In addition, as described above, since the defect density can be effectively reduced, the pn junction leakage current is sufficiently reduced.

The rate of temperature rise in the temperature lowering heat treatment after ion implantation is 10 ° C./sec or more, preferably 50 ° C./sec or more. Also, instead of such a rapid heat-up heat treatment,
After performing a heat treatment of about 500 to 600 ° C.,
Defect density can be effectively reduced even by performing the above high temperature treatment. Primary defects (point defects) are almost recovered by the first heat treatment, and completely recovered by the next high-temperature heat treatment.

(Fourth Embodiment) FIGS. 5A and 5B
FIG. 7 is a schematic diagram showing a main part (a part where a semiconductor substrate is installed) of a low-temperature ion implantation apparatus with a heat treatment function according to a fourth embodiment of the present invention. FIG. 5A is a view of the apparatus as viewed from above, and FIG. 5B is a schematic sectional view of the heating chamber along AA ′.

The main part of the low-temperature ion implantation apparatus is roughly divided into a beam line 11 through which the ion beam 10 passes.
And an end station 14 which is connected to the beam line 11 via an opening / closing valve 12, sets a semiconductor substrate (wafer) 13 to be irradiated with the ion beam 10, and has a cooling mechanism therein. This end station 14
And a heating chamber 16 for performing heat treatment (RTA). Incidentally, the ion beam 10 is formed by ion implantation means (not shown).

The cooling mechanism of the end station 14 includes a susceptor (not shown) on which the semiconductor substrate 13 is mounted or a rotating disk (not shown) on which the semiconductor substrate 13 is fixedly mounted.
A heat sink 17 for cooling the semiconductor substrate 13 provided in the heat sink 17, a pipe 18 through which a coolant passes through the heat sink 17, and a heat trap 19 whose surface temperature is lower than that of the heat sink 17. .

Even if the semiconductor substrate 13 is cooled by the heat trap 19, the end station 14
Frost due to H ₂ O remaining inside does not adhere to the semiconductor substrate 13. Since the adhesion of frost hinders the high-temperature heat treatment, it is preferable to prevent the frost from adhering.

The heat trap 19 is formed so as to cover at least a part of the side surface of the semiconductor substrate 13, and its shape can be various. For example, instead of the one shown in FIG. 5, a donut shape that continuously surrounds the semiconductor substrate 13 or a shape that discontinuously surrounds the semiconductor substrate 13 may be used.

With such a cooling mechanism, the semiconductor substrate 1
The temperature difference between the surface temperature of the substrate 3 and a mounting table such as a susceptor or a rotating disk on which the semiconductor substrate 13 is mounted can be kept within 10 ° C.

That is, the semiconductor substrate 13 can be cooled to the same degree as the mounting table, and the temperature of the surface of the semiconductor substrate 13 at the time of ion implantation can be set to a low temperature of -100 ° C. or less.

The transfer chamber 15 is provided with an exhaust system (not shown) so that the H ₂ O partial pressure can be set to 1 × 10 ⁻⁶ Torr or less. The evacuation system is, for example, a turbo molecular pump with a liquid nitrogen trap.
Further, similarly to the end station 14, a trap 20 is provided in the transfer chamber 15, thereby preventing frost on the semiconductor substrate 13 during transfer.

The heating chamber 16 has a heating source capable of heating the semiconductor substrate 13 at high speed. This heating source is, for example,
The substrate heater directly heats the semiconductor substrate 13 and the heater that heats the semiconductor substrate 13 by irradiation of infrared rays or ultraviolet rays. In the ion implantation apparatus of the present embodiment, the temperature of the surface of the semiconductor substrate 13 at the time of ion implantation can be sufficiently reduced by the cooling mechanism, so that generation of defect clusters can be prevented. In addition, since the temperature of the semiconductor substrate 13 can be increased at a high speed after the ion implantation, the effect is high.

Therefore, by using the ion implantation apparatus of this embodiment, it is possible to easily perform the ion implantation and heat treatment process in which the reduction in the substrate strength is minimized. Further, since the transfer of the semiconductor substrate 13 from the end station 14 to the heating chamber 16 is performed in a continuous vacuum, the ion implantation process and the heat treatment process are performed with higher reliability than when the ion implantation process and the heat treatment process are performed by separate apparatuses. A heat treatment step becomes possible.

The main part of the ion implantation apparatus is a measuring means 2 for measuring ions implanted into the semiconductor substrate 13.
3, an integrator 24 and a counter 25 are provided. These measures the total amount of ions implanted into the substrate 13,
Its measurement accuracy is higher than before. The reason is that the semiconductor substrate 1
This is because the generation of gas from the resist mask on the substrate 13 can be prevented by lowering the temperature of 3. Further, since the heat trap 19 is provided in the end station 14, the measurement accuracy is further ensured.

Next, a specific description will be given of an ion implantation method using the ion implantation apparatus configured as described above. First, the on-off valve 12 is opened, and the end station 14 is opened.
The semiconductor substrate 13 set therein is irradiated with the ion beam 10. At this time, the cooling mechanism lowers the substrate temperature to a low temperature (20 ° C. or lower, preferably −1
(Less than 00 ° C). In order to prevent charge-up of the semiconductor substrate 11 due to the implanted ions, it is preferable that the surface of the semiconductor substrate 13 be irradiated with low-energy electrons of 30 eV or less in advance during the ion implantation.

Next, the process proceeds to a heat treatment step for recovering an implantation loss (primary defect) due to ion implantation to a state close to perfection. That is, after the semiconductor substrate 11 into which the ions are implanted is continuously transferred to the heating chamber 16 through the transfer chamber 15 evacuated to a high vacuum, and the semiconductor substrate 11 is heated to a temperature higher than 700 ° C., for example, Heat treatment is performed. Inside the transfer chamber 15, a wafer handler coated with AlN is provided (not shown). The wafer handler has an electrostatic force or a pressure difference between the top and bottom of the wafer or a mechanical wafer chuck to hold the semiconductor substrate 13.

At this time, the temperature is preferably raised at a high speed of 10 ° C./sec or more. The reason for increasing the heating rate is that, when passing through a temperature range of 600 to 700 ° C. at a rate of 100 ° C./min or less, primary defects generated by ion implantation are likely to combine to form a defect cluster. This is because a secondary defect formed by growing a defect cluster is difficult to be recovered by heating at a temperature higher than 700 ° C.

In this embodiment, a method has been described in which the heat treatment is performed at a temperature higher than 700 ° C. at a high speed by passing through a halfway temperature range of about 600 to 700 ° C. at a high speed after the ion implantation. After the primary defect is recovered before the secondary defect grows by the following heat treatment, the final crystal defect may be recovered by a heat treatment at a temperature higher than 700 ° C. In the above description, the processing method of the ion implantation apparatus is not particularly described, but may be a single wafer type or a batch type. In the case of a single wafer type, the wafer (semiconductor substrate 13) is ion-implanted one by one, transported one by one, and heat-treated one by one in the heating chamber 16. In the case of the batch type, a plurality of wafers are simultaneously ion-implanted, a plurality of wafers are collected from a disk wheel into a wafer cassette, and then transferred to a wafer boat for a heating chamber to simultaneously heat the plurality of wafers.

In this embodiment, the case where the heat treatment is performed in the heating chamber 16 has been described.
7 may be provided with a heating mechanism, and after the ion implantation is completed, a heat treatment of heating the semiconductor substrate 13 to a temperature higher than 700 ° C. in the end station 14 may be performed.

(Fifth Embodiment) This embodiment is a modification of the second embodiment. First, a mask pattern (ion implantation mask) is formed which selectively covers a region of the Si substrate where ions are not to be implanted and has a thermal expansion coefficient approximately equal to the thermal expansion coefficient (about 3 ppm / K) of the Si substrate. I do.

The reason why such a mask pattern is used is that a mask pattern having a thermal expansion coefficient of 15 ppm / K or more is peeled off by thermal stress when cooled.

Next, the temperature of the substrate surface is set to a temperature lower than room temperature,
Preferably, while maintaining the temperature at -60 ° C or lower, the acceleration energy is about 20 to 40 keV, and the dose is 3 to 5 × 10
As ions 3 are implanted into the Si substrate 1 under the condition of ¹⁵ cm ^-2 . The primary defects caused by the ion implantation are point defects such as vacancies and interstitial atoms generated at the moment when As ions are implanted into the Si substrate. Here, the beam current is 10
By using a heat sink susceptor having a high thermal conductivity of about 20 mA, a state in which the temperature of the surface of the Si substrate is maintained at the above-described temperature during ion implantation is realized.

[0078] Next, the mask pattern (ion implantation mask), and the ions thereby generated by being irradiated the mask pattern was shaved, contaminants consisting of the constituent material of the mask pattern (e.g., C _x H _y ) is removed by oxygen plasma treatment. Next, in a nitrogen atmosphere,
When heat treatment is performed on the Si substrate at about 900 ° C. for 30 minutes, 1
The next defect is completely recovered.

Next, a second ion implantation is performed. At this time, as in the case of the first ion implantation, the temperature of the surface of the Si substrate is kept low during the ion implantation. Next, a second heat treatment (nitrogen atmosphere, 850 to 900)
C. for 30 minutes).

The secondary defects generated by the second ion implantation and heat treatment had only small dislocations. In the present embodiment, the same effect as in the second embodiment can be obtained. In addition, the method of the present embodiment is, for example, a CMOS method.
Is effective in the step of forming the n-type source / drain diffusion layers and the p-type source / drain diffusion layers. That is, it is effective when diffusion layers of different conductivity types are formed in different steps.

When the method of manufacturing a semiconductor device according to the present invention is used, the substrate strength remains at 5 even after the second ion implantation and heat treatment.
Since the pressure is not less than 00 MPa (see FIG. 3), the quality of the finally obtained semiconductor device can be improved as compared with the conventional case. For example, when cutting into chips, the adverse effects (cracks and the like) due to dicing can be further reduced than before. For example, in a resin-sealed package, the adverse effect of a force applied to a semiconductor device (chip) can be suppressed during heating for curing the resin or when the resin absorbs moisture. In particular, bare chip mounting is considered to be highly effective because there is less protection for the chip than before.

(Sixth Embodiment) This embodiment is an application of the fourth embodiment. First, features of the semiconductor manufacturing apparatus will be described with reference to the drawings.

FIG. 6 is a schematic plan view showing a main part of a low-temperature ion implantation apparatus having an asher and a heat treatment function according to a sixth embodiment of the present invention. The difference from FIG. 5 is that a chamber 26 (asher) for removing the resist is further connected to the transfer chamber 15. According to the present embodiment, ion implantation, mask removal,
Since the heat treatment can be performed continuously, the yield and characteristics of the semiconductor device can be improved.

Next, the manufacturing method will be described. A mask pattern (ion implantation mask) having a thermal expansion coefficient similar to the thermal expansion coefficient (about 3 ppm / K) of the Si substrate so as to selectively cover a region of the Si substrate where ions are not to be implanted first.
To form

Next, for ion implantation. The Si substrate is set on the end station 14. Ions such as As, B, and BF ₂ are implanted through the beam line chamber 11 while keeping the temperature lower than the surface of the Si substrate, preferably at a temperature of −60 ° C. or lower. After the ion implantation, the Si substrate is transferred to the chamber 26 via the transfer chamber 15. Then, the mask on the Si substrate is removed by, for example, O ₂ plasma.

Subsequently, a Si substrate is placed in the heating chamber 16 via the transfer chamber 15, and heat treatment is performed. Heat treatment condition is 700 ℃
Rapid heating (about 50 ° C./sec.) To a higher temperature is preferred.

According to the present embodiment, after ion implantation of the semiconductor substrate, the mask can be removed without being exposed to the outside air, and rapid heating can be performed. Therefore, the semiconductor substrate can be restored to a state before the ion implantation step.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the conditions were set so that the Si substrate strength was higher than the maximum stress in the Si substrate both during the ion implantation step and after the heat treatment step. Although it is lower than the maximum stress in the substrate, after the heat treatment step, the Si
Conditions may be set so that the substrate strength is higher than the maximum stress in the Si substrate. In addition, various modifications can be made within the technical scope of the present invention.

[0089]

As described above, according to the present invention,
By performing at least the ion implantation step under the condition that the critical stress at which the plastic deformation occurs in the semiconductor substrate becomes larger than the maximum stress in the semiconductor substrate, it is possible to effectively reduce the mechanical strength of the semiconductor substrate caused by the ion implantation step. Thus, a method of manufacturing a semiconductor device that can be prevented in a short time can be realized.

Further, according to the present invention, since the surface of the semiconductor substrate can be kept at a low temperature during ion implantation, a semiconductor manufacturing apparatus which can easily carry out the method of manufacturing a semiconductor device according to the present invention can be realized. Further, according to the present invention, a semiconductor device having mechanical strength equal to or more than a predetermined value can be obtained by using the above-described method for manufacturing a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a view showing a relationship between a substrate temperature and a defect density immediately after ion implantation and after heat treatment.

FIG. 2 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing the Si substrate strength and the maximum stress in the Si substrate in each step when an LSI is manufactured by using the method of the second embodiment.

FIG. 4 is a schematic view showing a main part of a low-temperature ion implantation apparatus with a heat treatment function according to a fourth embodiment of the present invention.

FIG. 5 is a schematic view showing a main part of a low-temperature ion implantation apparatus with a heat treatment function according to a fourth embodiment of the present invention.

FIG. 6 is a schematic view showing a main part of a low-temperature ion implantation apparatus with a heat treatment function according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing the Si substrate strength and the maximum stress in the Si substrate in each step when an LSI is manufactured by a conventional manufacturing method.

FIG. 8 is a view for explaining a problem of a conventional ion implantation / heat treatment method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Si substrate 2 ... Primary defect 3 ... Secondary defect 10 ... Ion beam 11 ... Beam line 12 ... Opening / closing valve 13 ... Semiconductor substrate 14 ... End station 15 ... Transfer chamber 16 ... Heating chamber 17 ... Heat sink 18 ... Piping 19, Reference Signs List 20: heat trap (frost adhesion preventing means) 23: measuring means 24: integrator 25: counter 26: chamber (asher)

Claims (16)

[Claims] An ion implantation step of implanting ions into a semiconductor substrate; and a heat treatment step of performing a heat treatment on the semiconductor substrate, wherein the semiconductor is formed after the heat treatment step, or during the ion implantation step and after the heat treatment step. A method of manufacturing a semiconductor device, wherein at least the conditions of the ion implantation step are set such that a critical stress at which a plastic deformation occurs in a substrate is larger than a maximum stress in the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the condition is that the ions are implanted into the semiconductor substrate while the surface temperature of the semiconductor substrate is maintained at a low temperature equal to or lower than a predetermined temperature. Of manufacturing a semiconductor device. 3. The method according to claim 2, wherein the predetermined temperature is 20 ° C. 4. The method according to claim 2, wherein the predetermined temperature is −100 ° C. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the condition of the heat treatment step is to increase a heating rate of the heat treatment. 6. The method according to claim 5, wherein the rate of temperature rise is 10 ° C./sec or more. 7. The method according to claim 1, wherein said ion implantation step and said heat treatment step are steps of forming a diffusion layer. 8. The method according to claim 1, wherein said ion implantation step and said heat treatment step are steps of forming shallow source / drain diffusion layers having a depth of 0.2 μm or less. 13. The method for manufacturing a semiconductor device according to item 5. 9. The method according to claim 1, wherein said ion implantation step and said heat treatment step are performed at least twice.
A method for manufacturing a semiconductor device according to claim 6. 10. An ion implanting means for implanting ions into a semiconductor substrate housed in a container, wherein the temperature of the surface of the semiconductor substrate is kept at a low temperature equal to or lower than a predetermined temperature when implanting ions into the semiconductor substrate. A semiconductor manufacturing apparatus comprising: a substrate temperature control unit; and a heat treatment unit for performing a heat treatment on the semiconductor substrate into which the ions have been implanted. 11. The semiconductor manufacturing apparatus according to claim 10, wherein said predetermined temperature is 20 ° C. 12. The semiconductor manufacturing apparatus according to claim 10, wherein said predetermined temperature is -100.degree. 13. The semiconductor manufacturing apparatus according to claim 10, wherein said heat treatment means performs a high-speed heat treatment on said semiconductor substrate. 14. The heating rate of said high-speed high-temperature heat treatment is 10
14. The semiconductor manufacturing apparatus according to claim 13, wherein the temperature is at least C / sec. 15. A frost adhesion preventing means for preventing frost due to residual H2O in the container from adhering to the surface of the semiconductor substrate when implanting ions into the semiconductor substrate held at the low temperature. The semiconductor manufacturing apparatus according to claim 10, wherein: 16. A semiconductor device having a diffusion layer of a different conductivity type or a diffusion layer of a different depth formed on a semiconductor substrate, wherein the maximum strength of the semiconductor substrate is 500 MPa.
A semiconductor device characterized by the above.