JPS576919A - Detecting circuit for faulty input pattern - Google Patents

Abstract

PURPOSE:To realize a monitor for a fault of an input pattern with a small number of component parts, by connecting the binary signals to the priority encoders of two series with the sequence of array of the binary signals made inverse to each other and then using an output obtained via an adding circuit for a decision of fault. CONSTITUTION:The input signals, e.g. 1-8 of a pattern in which only a binary signal secures a signal presence state in the normal mode are supplied to an OR element 10, and at the same time connected to priority encoders 11 and 12 of two series in such way that the sequence of array of binary signals becomes adverse to each other. The outputs of these encoders are supplied to an adding circuit that consists of an adder circuit 13, an AND element 14 and a reverse element 15 and generates the output signal of a pattern which follows an addition of each digit. Then a normal or fualty state of the input pattern is decided according to a signal presence or signal absence state of an AND16 of the element 15 and the output signal of the OR element 10. As a result, the number of AND elements is reduced, and a fault of an input pattern comprising a number of input signals can be monitored with a small number of component parts.